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mcux: add MIMXRT266x (i.MX RT266x) device and driver support - #813
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Bump hal_nxp to bring in the MIMXRT266x device data, power/memory controller components, and CCM rev3 clock IDs needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to bring in the MIMXRT266x device data, power/memory controller components, and CCM rev3 clock IDs needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to bring in the MIMXRT266x device data, power/memory controller components, and CCM rev3 clock IDs needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to bring in the MIMXRT266x device data, power/memory controller components, and CCM rev3 clock IDs needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to bring in the MIMXRT266x device data, power/memory controller components, and CCM rev3 clock IDs needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to bring in the MIMXRT266x device data, power/memory controller components, and CCM rev3 clock IDs needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to bring in the MIMXRT266x device data, power/memory controller components, and CCM rev3 clock IDs needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to bring in the MIMXRT266x device data, power/memory controller components, and CCM rev3 clock IDs needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to bring in the MIMXRT266x device data, power/memory controller components, and CCM rev3 clock IDs needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Support the new NXP i.MX RT266x family in the pinctrl SoC-header generator, for the Zephyr MIMXRT2660-EVK baseline bring-up. - IOMUX controller support. - RT266x pad-config register model and the 4-value fsl_iomuxc daisy fixup. - RT266x exposes three IOMUXC instances in separate power domains (MAIN, WAKE, VBAT); each pin is routed to its owning instance anchor (&iomuxc / &iomuxc_wake / &iomuxc_vbat) from the config-tools peripheral name, so no per-SoC anchor table is hardcoded. All RT266x-specific handling is gated on the part name, so the RT11xx path is unchanged. Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Generate the RT266x pinctrl devicetree for all 30 MIMXRT266x part numbers in
the config-tools data pack with gen_soc_headers.py, and let the generator's
dedup pass collapse the identical copies.
All 30 part numbers share one identical pin mux data set, so this leaves one
canonical file (mimxrt2663ahp8a-pinctrl.dtsi) and 29 one-line wrappers that
include it. Board devicetree includes are unaffected: each wrapper keeps its
own filename.
RT266x exposes three IOMUXC instances in separate power domains (MAIN, WAKE,
VBAT); the generator routes each pin to its owning instance anchor
(&iomuxc / &iomuxc_wake / &iomuxc_vbat) from the config-tools peripheral
name, so no per-SoC anchor table is hardcoded in the generator.
Generated with:
python mcux/scripts/pinctrl/gen_soc_headers.py <config-pack>.zip \
--copyright \
--iomuxc-file \
mcux/mcux-sdk-ng/devices/RT/RT2660/MIMXRT2663/drivers/fsl_iomuxc.h \
--soc-output dts/nxp
The daisy (select-input) column comes from the IOMUXC select-input candidate
lists in the pack's register data rather than from the signal configuration
file, which carries a DAISY assignment for only a subset of the pad/ALT pairs.
fsl_iomuxc.h is used as a cross-check: for this pack and the b260818 device
headers the two sources agree on all 700 entries, with no conflict and nothing
present in only one of them.
Three mux options (MAIN_XSPI0_ECS on PIO2_22 / PIO3_3 / PIO4_26) are named by
a select-input candidate list but absent from the signal configuration file's
<connections> data; the generator recovers those from the register data. Two
more (MAIN_XSPI0_TST_TRG / MAIN_XSPI1_TST_TRG on PIO3_30 / PIO3_31) exist in
fsl_iomuxc.h but are not described by the configuration data at all, so they
cannot be generated and are reported as a warning for an upstream data fix.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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The nxp,imx-ccm-rev3 clock controller takes packed devicetree cells whose root/gate/mux fields must equal the HAL enumerations it forwards them to (clock_lpcg_t, clock_root_t, clock_root_mux_source_t in fsl_clock.h). Keeping those ids by hand invites silent drift the moment a device release renumbers an enumerator, so generate them instead. The parsing framework is shared across the rev3 family; each SoC contributes a small socs/<soc>.py config naming its devicetree sub-directory and any enum naming exceptions. RT266x is the first, and needs no exceptions. The header is a hal_nxp artifact -- it is derived from this module's own fsl_clock.h -- so it is written into this module's devicetree root at dts/nxp/<family>/<series>/clock/, mirroring where the pinctrl artifacts are generated, and consumed from devicetree as #include <nxp/<family>/<series>/clock/imx_ccm_rev3_<soc>.h>. Nothing is written into the zephyr tree; only the SoC-agnostic packed-cell header <zephyr/dt-bindings/clock/imx_ccm_rev3.h> lives there. --check regenerates in memory and byte-compares against the committed header, exiting 1 on drift, which is what keeps the checked-in ids honest. The FSL_CLOCK_DRIVER_VERSION is recorded to explain why a header went stale but is deliberately not used to skip the byte comparison: NXP has changed enumerators without bumping it. Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Generate imx_ccm_rev3_rt266x.h from the MIMXRT2663 fsl_clock.h with gen_ccm_rev3_ids.py, giving devicetree the 832 IMX_CCM_LPCG_* / IMX_CCM_ROOT_* / IMX_CCM_MUX_* macros the nxp,imx-ccm-rev3 controller consumes. One file per SERIES, not per part number: RT2660 and RT2663 share one CCM, so their root, gate and mux ids are identical and a per-part split would create two copies that must agree. This differs from pinctrl deliberately -- pin availability genuinely varies by package, clock root topology does not. Do not edit by hand; regenerate with the script and let --check keep it honest. Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to bring in the MIMXRT266x device data, power/memory controller components, and CCM rev3 clock IDs needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to the RT266x baseline revision which adds the generated pinctrl devicetree and the CCM rev3 clock-ID header needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Bump hal_nxp to the RT266x baseline revision which adds the generated pinctrl devicetree and the CCM rev3 clock-ID header needed for the RT266x SoC series and MIMXRT2660-EVK board. zephyrproject-rtos/hal_nxp#813 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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Add HAL support for the i.MX RT266x SoC series (MIMXRT2660/2661/2662/2663),
enabling the MIMXRT2660-EVK baseline bring-up in Zephyr.
Changes
gen_soc_headersfor the RT266xcombined PIO register model; restructure pinctrl DTS into family/series layout
mcux: devices: RT2660) — CMSIS headers,system_*,per-device drivers (
fsl_clock,fsl_reset,fsl_memory,fsl_edma_soc),and periph headers for all four parts; device data taken from
mcux-devices-rt@ 26.09.00 RC1 tagmcux: drivers: RT2660) —powerconandrt2k_pmucomponents required byPOWER_SetPolicy()script that produces it
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