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rw612: Fix SCTIMER offset overflow in pinctrl definitions - #633
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dragomirecky wants to merge 1 commit into
Open
dragomirecky wants to merge 1 commit into
dragomirecky wants to merge 1 commit into
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The SCTIMER_IN/OUT_CLR offset fields were using only 3 bits (max value 7), but some GPIO pins require SCTIMER offsets 8 and 9, causing truncation and incorrect pin configuration.
mmahadevan108
requested review from
EmilioCBen,
decsny,
dleach02 and
mmahadevan108
November 5, 2025 15:17
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|
Seems related to zephyrproject-rtos/zephyr#99007 |
| #define IOMUX_CTIMER_CLR(offset, enable)\ | ||
| IOMUX_OFFSET_ENABLE(offset, enable, 8) | ||
| #define IOMUX_FSEL_CLR(mask) ((mask) << 13) | ||
| IOMUX_OFFSET_ENABLE(offset, enable, 10) |
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Any reason you went to 10 instead of 9
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This PR is not really meant to be merged, as the edited file starts with a note that it was generated by "parse_iomux.py". I couldn't find it anywhere. I would have created just an Issue, but this repo doesn't have them enabled.
The problem: SCTIMER_IN/OUT_CLR offset fields are using only 3 bits (max value 7), but some GPIO pins require
SCTIMER offsets 8 and 9, causing truncation and incorrect pin configuration.
To fix this, one extra bit needs to be allocated for the offset fields (as in this PR). Similar change needs to be done in Zephyr's
soc/nxp/rw/pinctrl_defs.h.Feel free to tell me if there is a way I can contribute those changes properly.