Fixing buffers in vmul/vmacc and its variants

[Joao-Pedro-Cabral]

This PR fix the following bug:

• Internal multiplier and accumulator block buffers doesn’t respect pipeline stalls (always update);

[ParkerJones567]

This behavior has already been fixed as part of Vicuna2.0. Please upgrade to the current development repository here:

https://github.com/vproc/vicuna2_core

[Joao-Pedro-Cabral]

Sorry, can you explain for me how should I integrate vicuna2_core with vicuna environment?
Because vicuna2_core doesn't contain the simulation and tests folders from vicuna.

[Joao-Pedro-Cabral]

Moreover, your fix misses this bug:

-assign res_d = acc_sub_i ? {17'b0, acc_q} - mul_q : {17'b0, acc_q} + mul_q;
+assign res_d = acc_sub_q ? {17'b0, acc_q} - mul_q : {17'b0, acc_q} + mul_q;

[ParkerJones567]

vicuna2_core contains the rtl, which should be a drop in replacement for the rtl in the original environment. You may have to update some makefiles.

A reworked test environment is being developed currently (including more robust unit tests). It should be made public soon.

[ParkerJones567]

Can you provide an assembly example to reproduce this bug?

Moreover, your fix misses this bug:

-assign res_d = acc_sub_i ? {17'b0, acc_q} - mul_q : {17'b0, acc_q} + mul_q;
+assign res_d = acc_sub_q ? {17'b0, acc_q} - mul_q : {17'b0, acc_q} + mul_q;

[Joao-Pedro-Cabral]

I found this bug when debugging my research code (which is very big), and I didn't remember where exactly the bug happened.

My source code will probably be public available in one month.

However, I will see if I can found an assembly example for you, as soon as possible.

Can you provide an assembly example to reproduce this bug?

Moreover, your fix misses this bug:

-assign res_d = acc_sub_i ? {17'b0, acc_q} - mul_q : {17'b0, acc_q} + mul_q;
+assign res_d = acc_sub_q ? {17'b0, acc_q} - mul_q : {17'b0, acc_q} + mul_q;