[ENCODEGEN,ARM64] Remove x86 instruction in ARM64 encoder template

[TechnoPorg]

I came across this while working on rustc_codegen_tpde, whose TPDE patches I'll be working on upstreaming this week.

[aengelke]

How did you hit this? AArch64 should have no relevant instructions with operand constraints to a single register.

[TechnoPorg]

This showed up during one of my earlier attempts at 128-bit float to integer conversion, which generated the following code:

    // # Machine code for function f32toi128: NoPHIs, TracksLiveness, NoVRegs, TiedOpsRewritten, TracksDebugUserValues
    // Frame Objects:
    //   fi#0: size=8, align=16, at location [SP-16]
    // Function Live Ins: $s0
    // 
    // bb.0 (%ir-block.1):
    //   liveins: $s0, $lr
    //   early-clobber $sp = frame-setup STRXpre killed $lr, $sp(tied-def 0), -16 :: (store (s64) into %stack.0)
    //   BL &__fixsfti, <regmask $fp $lr $wzr $wzr_hi $xzr $b8 $b9 $b10 $b11 $b12 $b13 $b14 $b15 $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $h8 $h9 $h10 $h11 $h12 $h13 $h14 $h15 $s8 $s9 $s10 $s11 and 92 more...>, implicit-def dead $lr, implicit $sp, implicit killed $s0, implicit-def $sp, implicit-def $x0, implicit-def $x1
    //   early-clobber $sp, $lr = frame-destroy LDRXpost $sp(tied-def 0), 16 :: (load (s64) from %stack.0)
    //   RET undef $lr, implicit killed $x0, implicit killed $x1
    // 
    // # End machine code for function f32toi128.

Until your comment prompted me to remember why I had made this change, I had not realized that TPDE compiles without it now that I've moved away from encode_template.c for float to int conversion.

[T0b1-iOS]

I removed the code in d3e9e59. Fixed register do not exist on AArch64 for the purposes of encodegen.