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[ROCm] Support packed INT4x2/UINT4x2 codegen #3103

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[ROCm] Support packed INT4x2/UINT4x2 codegen #3103

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286d000
[ROCm] Support packed int4x2 codegen
andyluo7 Aug 27, 2026
5b284c8
[ROCm] Enforce packed 4-bit byte ownership
andyluo7 Aug 27, 2026
2367355
[ROCm] Address packed INT4 review findings
andyluo7 Aug 27, 2026
d76c011
[ROCm] Validate packed copy ownership after remap
andyluo7 Aug 27, 2026
4ac080f
[ROCm] Validate packed local copy and im2col ownership
andyluo7 Aug 27, 2026
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80 changes: 52 additions & 28 deletions src/op/copy.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,10 @@

#include "copy.h"
#include "../transform/common/loop_fusion_utils.h"
#include "../transform/common/storage_size.h"
#include "../transform/loop_partition.h"
#include "../transform/loop_vectorize.h"
#include "backend/common/target_utils.h"
#include "span_utils.h"
#include "support/check.h"
#include "utils.h"
Expand All @@ -30,14 +32,40 @@ namespace tl {
using namespace tirx;
using namespace ffi;

namespace {

bool IsPacked4BitNonLocalBuffer(const Buffer &buffer) {
return (IsGlobalBuffer(buffer) || IsSharedBuffer(buffer)) &&
buffer->dtype.lanes() == 1 && IsPacked4BitStorage(buffer->dtype);
}

ParallelOp InferGeneratedParallelOp(const For &loop,
const LowerArgs &lower_args,
arith::Analyzer *analyzer) {
auto par_op = ParallelOp(loop);
std::vector<InferLevel> levels = {InferLevel::kCommon, InferLevel::kStrict,
InferLevel::kFree};
for (auto level : levels) {
par_op->InferLayout({lower_args.target,
lower_args.thread_bounds,
lower_args.layout_map,
analyzer,
lower_args.buffer_remap,
{}},
level);
}
return par_op;
}

} // namespace

Stmt LowerNormalCopy(const CopyNode &op, const LowerArgs &lower_args,
arith::Analyzer *analyzer) {
bool is_cpu_target = lower_args.target->GetTargetDeviceType() == kDLCPU;
auto simt_loop = op.MakeSIMTLoop(analyzer);
auto fused_loop = Downcast<For>(ParallelLoopFuser::Fuse(simt_loop));

For vectorized_thread_loop;
auto par_op = ParallelOp(fused_loop);

if (is_cpu_target || IsLocalBuffer(op.src) || IsLocalBuffer(op.dst)) {
if (IsLocalBuffer(op.src) && !IsLocalBuffer(op.dst)) {
Expand Down Expand Up @@ -67,26 +95,27 @@ Stmt LowerNormalCopy(const CopyNode &op, const LowerArgs &lower_args,
<< "` may cause conflicted write.";
}
}
if (TargetIsRocm(lower_args.target) && IsPacked4BitNonLocalBuffer(op.dst)) {
ValidatePacked4BitStoreOwnership(
fused_loop, lower_args.thread_index, lower_args.thread_bounds,
analyzer, lower_args.buffer_remap, lower_args.layout_map);
}
vectorized_thread_loop = VectorizeLoop(fused_loop, lower_args.layout_map);
return vectorized_thread_loop;
}

std::vector<InferLevel> levels = {InferLevel::kCommon, InferLevel::kStrict,
InferLevel::kFree};
for (auto level : levels) {
par_op->InferLayout({lower_args.target,
lower_args.thread_bounds,
lower_args.layout_map,
analyzer,
lower_args.buffer_remap,
{}},
level);
}
auto par_op = InferGeneratedParallelOp(fused_loop, lower_args, analyzer);
auto loop_layout = par_op->GetLoopLayout();
Optional<PrimExpr> predicate = par_op->GetPredicate(lower_args.thread_index);
if (TargetIsRocm(lower_args.target)) {
ValidatePacked4BitStoreOwnership(
par_op->GetRoot(), loop_layout, lower_args.thread_index, analyzer,
predicate, lower_args.buffer_remap, lower_args.layout_map);
}
return LowerParallelLoop(
par_op->GetRoot(), loop_layout, lower_args.thread_index, analyzer,
lower_args.layout_map, par_op->GetPredicate(lower_args.thread_index),
/*parallel_loop=*/true, par_op->LoopLayoutRequiresPaddingGuard());
lower_args.layout_map, predicate, /*parallel_loop=*/true,
par_op->LoopLayoutRequiresPaddingGuard());
}

namespace {
Expand Down Expand Up @@ -245,23 +274,18 @@ Stmt LowerIm2ColSIMT(const Im2ColOpNode &op, const LowerArgs &lower_args,
body = For(i, make_zero(i.dtype()), block_m, ForKind::kParallel, body);

auto fused_loop = Downcast<For>(ParallelLoopFuser::Fuse(Downcast<For>(body)));
auto par_op = ParallelOp(fused_loop);
std::vector<InferLevel> levels = {InferLevel::kCommon, InferLevel::kStrict,
InferLevel::kFree};
for (auto level : levels) {
par_op->InferLayout({lower_args.target,
lower_args.thread_bounds,
lower_args.layout_map,
analyzer,
lower_args.buffer_remap,
{}},
level);
}
auto par_op = InferGeneratedParallelOp(fused_loop, lower_args, analyzer);
auto loop_layout = par_op->GetLoopLayout();
Optional<PrimExpr> predicate = par_op->GetPredicate(lower_args.thread_index);
if (TargetIsRocm(lower_args.target) && IsPacked4BitNonLocalBuffer(dst)) {
ValidatePacked4BitStoreOwnership(
par_op->GetRoot(), loop_layout, lower_args.thread_index, analyzer,
predicate, lower_args.buffer_remap, lower_args.layout_map);
}
return LowerParallelLoop(
par_op->GetRoot(), loop_layout, lower_args.thread_index, analyzer,
lower_args.layout_map, par_op->GetPredicate(lower_args.thread_index),
/*parallel_loop=*/true, par_op->LoopLayoutRequiresPaddingGuard());
lower_args.layout_map, predicate, /*parallel_loop=*/true,
par_op->LoopLayoutRequiresPaddingGuard());
}

bool RegisterDefaultIm2Col() {
Expand Down
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