riscv32-cosim-model

• Prerequisites
  • Optional
• Getting Started
• Building and Running
  • Simulation
  • Synthesis
  • Intel JTAG UART
• Contributing
• Authors
• License
• Acknowledgements
  • External

A work-in-progress RISC-V 32-bit co-simulation model. It includes RTL of a developing RISC-V core design, UVM testbenches, and SystemVerilog DPI (svdpi) interfaces to communicate with the C++ code from the associated projects riscv32-decoder and riscv32-sim.

Prerequisites

Before you begin, ensure you have met the following requirements:

• Vivado 20xx.x
• XSIM
• C/C++ compiler
• make
• p7zip or any other software that supports v2.0 DEFLATE can be used. If you decide to use a different software, you will need to adjust data/Makefile accordingly.
• jq
• perl

Optional

To use Easier UVM perl script you'll need:

• perl>=5.8.0.
• the following packages, which can be installed either through CPAN or your distribution's package manager:

use File::Copy::Recursive qw(dircopy);
use File::Copy "cp";
use File::stat;

Getting Started

1. Clone the repository

git clone --recursive https://github.com/ssayin/riscv32-cosim-model.git

2. Navigate to the directory

cd riscv32-cosim-model

If you have already cloned the repository, you can fetch the submodules with:

git submodule update --init --recursive

Building and Running

Simulation

This project uses a Makefile for building and running the co-simulation model. The Makefile provides several targets for different tasks:

• libdpi.so: Compile the shared library that exposes riscv32-decoder routines.

• compile: Compile the SystemVerilog files using the Xilinx Vivado Suite.

• clean: Remove all generated files from the previous build.

Please check Makefile for further details.

To build and run the project, follow these steps:

1. Open a terminal in the project root directory.

2. Run the following program:

make sim

4. To clean the project (remove all generated files), enter the following command:

make clean

Synthesis

./tools/intel_synth.sh

Intel JTAG UART

To build and run the UART tool, follow these steps:

1. Set the QUARTUS_ROOT environment variable to the path of your Quartus installation. For example, if you're using Quartus version 22.1 Lite and it's installed at /opt/intelFPGA_lite/22.1std/quartus/, you can set it using the following command:

export QUARTUS_ROOT=/opt/intelFPGA_lite/22.1std/quartus/

2. Build the UART client by running the following program:

make QUARTUS_ROOT=$QUARTUS_ROOT uart_client

Important: Whenever you open a new shell session to work with the UART tool, remember to reset the LD_LIBRARY_PATH using the previously defined QUARTUS_ROOT value. Exporting this variable in a file sourced by your shell i.e. your .bashrc can save you time.

3. Edit the ./tools/uart file and adjust the LD_LIBRARY_PATH variable to include $QUARTUS_ROOT:

LD_LIBRARY_PATH=$QUARTUS_ROOT uart_client $@

4. Run the program:

./tools/uart Hi

Replace "Hi" with whichever message you want to transmit. If no argument string is provided, the program reads from stdin.

echo "Hi" | ./tools/uart

Contributing

If you would like to contribute, please fork the repository and submit a pull request. For major changes, please open an issue first to discuss what you would like to change.

Authors

• Serdar Sayın

License

This project is licensed under the Apache 2.0 License - see the LICENSE file for details.

Acknowledgements

I would like to thank the RISC-V community for their comprehensive ISA specification, which made this project possible.

External

• alterajtaguart by thotypous: Disassembling jtag_atlantic.so and providing an associated API.

• jtag_uart_example by tomverbeure: Providing examples for integrating the Intel JTAG UART API into projects.