Implement mixed-size access in UM promising model#98
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This is good work! There are still some kinks to iron out both in the fiddly part of the mixed-semantics and in general organization, but I think this is close to being mergeable
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Some nit-picks, and the main semantic of read_mem is still wrong (but it's really tricky)
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The main logic for mix-sized accesses is correct,
All those comments are more about cleanup/simplification/comment improvements except for a minor one in the exclusives semantics
- Msg.t: dependent record with `val : bv (8 * size)` so all messages share one list - Multi-byte reads: single observation point per load - Exclusive monitor: stores LDXR addr/size, mismatch is non-deterministic (ARM ARM B2.12) - CBitvector: vm_compute-friendly bv_eq_dec/countable/finite replacing stdpp's opaque versions - GenPromising: mEvent_eqb / remove_dups_by to bypass eq_dec blocking under vm_compute
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Summary
Msg.tis now a dependent record withval : bv (8 * size)so all messages live in one list