examples/sim: add shift(-right) register examples

[HarryMakes]

Edit: 2020-10-14: changed types from "parallel-in" and "serial-in" to with and without input/output enable strobes.

---

Overview

This PR introduces possible shift register implementations, in the hope of boosting the learning experience for Migen users.

Details

2 examples are introduced to implement 2 possible types of a shift-right register.

• sr1.py: Implementation of shift-right register that begins shifting at reset (i.e. input and output are always enabled).

• sr2.py: Implementation of shift-right register whose shifting action is controlled by an input and an output strobe.

For each type, 2 examples showing different modes of shift registers are provided. All these examples are 8-bit shift registers. The two modes are:

• Parallel-In, Serial-Out: Input is 8-bit wide while output is 1-bit wide, shifting out 1 bit of a complete input value from LSB (bit 0) to MSB (bit 7) at a time.

  • Initially, once input is enabled, the input should contain all bits of a value to be stored in the next clock cycle.
  • When output is kept enabled, the output bit position will be advanced by 1 in the next clock cycle (i.e. from bit 0 to bit 1, from bit 7 to bit 0, etc.) such that the next bit of the currently stored value will be shifted out in the next clock cycle.
  • If both input and output are enabled, once the final bit (bit 7) of the current value has been shifted out, the new value at the input would also have been shifted in.

• Serial-In, Parallel-Out: Input is 1-bit wide, shifting in 1 bit of a value from LSB (bit 0) to MSB (bit 7) at a time, while output is 8-bit wide.

  • Initially, when input is kept enabled, the input bit position will be advanced by 1 in the next clock cycle (i.e. from bit 0 to bit 1, from bit 7 to bit 0, etc.) such that the input should contain the next bit of a value to be stored in the next clock cycle. This means any bit of the input does not need to be finalised until it gets shifted in.
  • Once output is enabled, the currently stored value will be shifted out bit by bit (from LSB to MSB) in the next clock cycle. For example, if bit 2 is to be shifted out, the bit positions 5 to 7 of the output will contain bits 0 to 2. The output is complete when the MSB has been shifted out as output bit 7, signaled with an "output valid" strobe.
  • If both input and output are enabled, once "output valid" is asserted, the new value at the input begins to be shifted in in the next clock cycle.

[HarryMakes]

Reimplemented the examples with 1fb3a5a.

Styling should be improved if this PR is approved.