A big thanks to @TiberiuBucur . we find a potential bug in diyone7 in mixed/fullmixed mode.
(* diyone7 -hexa -arch AArch64 -variant fullmixed -metadata false -oneloc PosRW X h0 Rfi *)
AArch64 CoRW1+posw0x.h0-rfix.h0w0
Variant=mixed
{
uint32_t 0:X0=0; 0:X1=x;
}
P0 ;
LDR W0,[X1] ;
MOV W2,#257 ;
Loop00: ;
LDXRH W3,[X1] ;
STXRH W4,W2,[X1] ;
CBNZ W4,Loop00 ;
exists ([x]=0x101 /\ 0:X0=0x101 /\ 0:X3=0x100)
The post condition 0:X3=0x100 is incorrect which should be 0:X3=0. This reflect the scenario LDXRH and STXRH can be reordered before LDR. It is likely due to X use 0x101 - 1 to infer the LDXRH value. However in mixed mode, the value should be per-byte-based.
A big thanks to @TiberiuBucur . we find a potential bug in
diyone7inmixed/fullmixedmode.The post condition
0:X3=0x100is incorrect which should be0:X3=0. This reflect the scenarioLDXRHandSTXRHcan be reordered beforeLDR. It is likely due toXuse0x101 - 1to infer theLDXRHvalue. However inmixedmode, the value should be per-byte-based.