core: Add buffers to IP and ICMP

[rowanG077]

This significantly improves timing on ECP5. This allows ECP5 to once again reach 50Mhz with ease.

It does burn a few FFs and LUTs though On a UDP echo design on a 25k ECP5 we go from

Info:             TRELLIS_FF:  2334/24288     9%
Info:           TRELLIS_COMB:  5432/24288    22%
Info:           TRELLIS_RAMW:   136/ 3036     4%

to

Info:             TRELLIS_FF:  2570/24288    10%
Info:           TRELLIS_COMB:  5752/24288    23%
Info:           TRELLIS_RAMW:   136/ 3036     4%

So if you want to make this configurable @enjoy-digital let me know

[enjoy-digital]

I did a fresh timing sweep on current master using bench/colorlight_5a_75b.py on LFE5U-25F-6BG256C, Trellis, seed 1. All edits were local experiments and were reverted afterward.

Baseline:

eth_rx max: 60.71 MHz  (fails 125 MHz)
sys max:    63.23 MHz  (passes 50 MHz)
FF/COMB/RAMW: 3323 / 5436 / 149

Tested variants:

#151-style IP+ICMP buffers, pipe_ready=False:
  eth_rx 68.12 MHz, sys 63.63 MHz, 3506 FF / 5440 COMB / 149 RAMW

IP+ICMP buffers, pipe_valid=True, pipe_ready=True:
  eth_rx 73.56 MHz, sys 62.34 MHz, 3691 FF / 5508 COMB / 149 RAMW

IP-only RX buffer, pipe_valid=True, pipe_ready=True:
  eth_rx 73.24 MHz, sys 59.17 MHz, 3458 FF / 5441 COMB / 149 RAMW

IP-only ready-only buffer, pipe_valid=False, pipe_ready=True:
  eth_rx 68.25 MHz, sys 64.23 MHz, 3391 FF / 5540 COMB / 149 RAMW

UDP RX CDC buffered:
  eth_rx 57.78 MHz, sys 61.51 MHz, 3412 FF / 5473 COMB / 149 RAMW

UDP RX source buffer, pipe_valid=True, pipe_ready=True:
  eth_rx 56.38 MHz, sys 63.98 MHz, 3474 FF / 5516 COMB / 149 RAMW

ICMP disabled:
  eth_rx 66.66 MHz, sys 59.82 MHz, 3019 FF / 4763 COMB / 123 RAMW

I also tried the architectural direction of moving the protocol stack to the sys side with data_width=32. With seed 1 it closed both clocks:

eth_rx max: 131.80 MHz
sys max:    51.30 MHz
FF/COMB/RAMW: 3089 / 6277 / 150

But it was not robust across seeds: seed 2 gave 109.11 MHz / 48.52 MHz, and seed 3 gave 122.09 MHz / 49.88 MHz.

Conclusion: the original idea is directionally useful, but #151 as-is only registers the forward path (pipe_ready=False), leaving much of the back-pressure timing path intact. The best narrow code experiment was an IP RX -> IP crossbar buffer with both pipe_valid=True and pipe_ready=True; it improves ECP5 timing materially with modest area cost, but does not close 125 MHz on this target. For actual ECP5 closure, the larger direction seems to be keeping the full UDP/IP/Etherbone stack out of the 125 MHz RX domain, then tightening the remaining MAC RX CDC/sys-domain paths.

[rowanG077]

Sure the important thing is that you need to keep the main core outside of the 125Mhz domain AND also require these buffers. The important config in this case was completely overlooked.

I vaguely remember some other PR also adding these buffers somewhere but I can't find it quickly.