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V5 Fix big endian and 32bit builds#2943

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Rot127 merged 19 commits into
capstone-engine:v5from
trufae:v5-be
Jun 4, 2026
Merged

V5 Fix big endian and 32bit builds#2943
Rot127 merged 19 commits into
capstone-engine:v5from
trufae:v5-be

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@trufae trufae commented May 29, 2026

i backported the crossbuilds ci jobs from the next branch to the v5 one.

that confirmed the bugs i found that are already fixed in v6, so i just fixed them here and added more tests:

  • mos65xx UB with format strings on 32bit (causing segfault on arm thumb runner)
  • m68k UB in printf missing cast (causing invalid output in the disassembler)
  • big endian bug in the x86 sib calculation causing some x86 instructions to disassemble incorrectly

@github-actions github-actions Bot added X86 Arch M68K Arch MOS65XX Arch Github-files Github related files labels May 29, 2026
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Would you mind also applying the other changes from https://github.com/capstone-engine/capstone/pull/2796/changes#diff-8ab50bbaa9a6956702fed253c6b8d13be8f3c4b062faf4398af2053c731e9e82

There are not that many. Mostly formatting changes for the three archs here. Simply copy and paste should do the job.

Comment thread tests/test_arm64.c
Comment thread .github/workflows/CrossBuilds.yml Outdated
Comment thread .github/workflows/CrossBuilds.yml
Comment thread .github/workflows/CrossBuilds.yml Outdated
Comment thread .github/workflows/CrossBuilds.yml Outdated
trufae and others added 3 commits May 29, 2026 23:30
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
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trufae commented Jun 1, 2026

done. do u want me to rewrite the history in separate commits for clarity about fixes/features or do you prefer to do that yourself?

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/usr/lib/gcc-cross/mips-linux-gnu/12/../../../../mips-linux-gnu/bin/ld: /tmp/ccHbECYk.o: in function `set_function':
capstone_test.c:(.text+0xee4): undefined reference to `get_detail_sh'
collect2: error: ld returned 1 exit status

It doesn't look like cstest is build successfully.
And the report.py script just ignores that :(

v5 testing is pretty broken...

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trufae commented Jun 2, 2026

Sorry for the mess, but it seems like it's finally going well now

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Rot127 commented Jun 2, 2026

Sadly not :(

[-] There are/is 36 failed test(s)
[-] Detailed report for suite/MC/AArch64/basic-a64-instructions.s.cs:

	[+] Line 470: 0xe3,0xff,0xff,0xb5
		"cbnz x3, #0xfffffffffffffffc" != "cbnz x3, #-4" ( "cbnz x3, #18446744073709551612" != "cbnz x3, #4294967292" and "cbnz x3, #18446744073709551612" != "cbnz x3, #4294967292" )

	[+] Line 472: 0x1f,0x00,0x80,0xb5
		"cbnz xzr, #0xfffffffffff00000" != "cbnz xzr, #-1048576" ( "cbnz xzr, #18446744073708503040" != "cbnz xzr, #4293918720" and "cbnz xzr, #18446744073708503040" != "cbnz xzr, #4293918720" )

	[+] Line 474: 0xeb,0xff,0xff,0x54
		"b.lt #0xfffffffffffffffc" != "b.lt #-4" ( "b.lt #18446744073709551612" != "b.lt #4294967292" and "b.lt #18446744073709551612" != "b.lt #4294967292" )

	[+] Line 868: 0x0a,0x00,0x80,0x58
		"ldr x10, #0xfffffffffff00000" != "ldr x10, #-1048576" ( "ldr x10, #18446744073708503040" != "ldr x10, #4293918720" and "ldr x10, #18446744073708503040" != "ldr x10, #4293918720" )

	[+] Line 1042: 0x6a,0x04,0x10,0x38
		"strb w10, [x3], #0xffffffffffffff00" != "strb w10, [x3], #-256" ( "strb w10, [x3], #18446744073709551360" != "strb w10, [x3], #4294967040" and "strb w10, [x3], #18446744073709551360" != "strb w10, [x3], #4294967040" )

	[+] Line 1045: 0x6a,0x04,0x10,0x78
		"strh w10, [x3], #0xffffffffffffff00" != "strh w10, [x3], #-256" ( "strh w10, [x3], #18446744073709551360" != "strh w10, [x3], #4294967040" and "strh w10, [x3], #18446744073709551360" != "strh w10, [x3], #4294967040" )

	[+] Line 1048: 0x95,0x05,0x10,0xb8

Sorry for the mess

Not really your fault. The testing in v5 is just not nice to use.
That is why it is completely redone in v6.

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Rot127 commented Jun 3, 2026

Only one left:

[-] There are/is 3 failed test(s)
[-] Detailed report for suite/MC/AArch64/basic-a64-instructions.s.cs:

	[+] Line 1394: 0xe5,0x59,0x0f,0xd5
		"sys #7, c0, c0, #7, x5" != "sys #7, c5, c9, #7, x5" ( "sys 7, c0, c0, 7, x5" != "sys 7, c5, c9, 7, x5" and "sys 7, c0, c0, 7, x5" != "sys 7, c5, c9, 7, x5" )

	[+] Line 1396: 0xe9,0x59,0x2f,0xd5
		"sysl x9, #7, c0, c0, #7" != "sysl x9, #7, c5, c9, #7" ( "sysl x9, 7, c0, c0, 7" != "sysl x9, 7, c5, c9, 7" and "sysl x9, 7, c0, c0, 7" != "sysl x9, 7, c5, c9, 7" )

	[+] Line 1397: 0x41,0xff,0x28,0xd5
		"sysl x1, #0, c0, c0, #2" != "sysl x1, #0, c15, c15, #2" ( "sysl x1, 0, c0, c0, 2" != "sysl x1, 0, c15, c15, 2" and "sysl x1, 0, c0, c0, 2" != "sysl x1, 0, c15, c15, 2" )



Check out my 32bit PR for the next branch.
I remember fixing it there.

@github-actions github-actions Bot added the AArch64 Arch label Jun 3, 2026
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trufae commented Jun 3, 2026

good now?

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Rot127 commented Jun 3, 2026

Thanks, will do a last swipe tomorrow.

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lgtm. Please rebase and we can merge.

Never mind. I did it quickly.

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trufae commented Jun 4, 2026

The commit history is messed up with random fixes here and there, will you squash or want to me remake the commits in a clean way?

@Rot127 Rot127 changed the title V5 be V5 Fix big endian and 32bit builds Jun 4, 2026
@Rot127 Rot127 merged commit c04e7f2 into capstone-engine:v5 Jun 4, 2026
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Rot127 commented Jun 4, 2026

We squash here normally. I fixed the commit message.
Thanks a lot!

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