[ATfE] Implement __arm_sme_state in LLVM libc bootcode#849
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This adds LLVM libc bootcode support for __arm_sme_state as per https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#811__arm_sme_state to match this LLVM change llvm/llvm-project#191434
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@MacDue @sdesmalen-arm please review __arm_sme_state for LLVM libc, thanks! |
MacDue
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May 11, 2026
| " /* Check whether SME or SME2 is present. */\n" | ||
| " mrs x16, id_aa64pfr1_el1\n" | ||
| " tst w16, #0x3000000\n" | ||
| " b.eq .L__arm_sme_state_no_sme\n" |
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Do we want to TODO/FIXME to handle this similar to picolibc/newlib? i.e., avoiding re-checking id_aa64pfr1_el1 in user code.
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| asm volatile("mrs %0, s3_4_c1_c2_6" : "=r"(smcr)); | ||
| smcr = (smcr & ~0xfUL) | 0xfUL; | ||
| asm volatile("msr s3_4_c1_c2_6, %0\n\tisb" : : "r"(smcr) : "memory"); |
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Question: Should picolib/newlib also handle the EL2 case?
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picolibc assumes it is running at EL1, LLVM libc boot code here can run at EL2 and EL3.
vhscampos
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May 11, 2026
Add new system register wrappers: TPIDR2 https://developer.arm.com/documentation/ddi0601/2026-03/AArch64-Registers/TPIDR2-EL0--EL0-Read-Write-Software-Thread-ID-Register-2 SVCR https://developer.arm.com/documentation/ddi0601/2026-03/AArch64-Registers/SVCR--Streaming-Vector-Control-Register SMCR_EL2 https://developer.arm.com/documentation/ddi0601/2026-03/AArch64-Registers/SMCR-EL2--SME-Control-Register--EL2- SMCR_EL3 https://developer.arm.com/documentation/ddi0601/2026-03/AArch64-Registers/SMCR-EL3--SME-Control-Register--EL3- ID_AA64PFR1 https://developer.arm.com/documentation/ddi0601/2026-03/AArch64-Registers/ID-AA64PFR1-EL1--AArch64-Processor-Feature-Register-1
vhscampos
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May 18, 2026
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It looks really good now. Thanks for the updates
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Thank you for the review and confirmation! @MacDue any more comments from your side? |
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This adds LLVM libc bootcode support for __arm_sme_state as per https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#811__arm_sme_state to match this LLVM change llvm/llvm-project#191434