fix: sim7080g module - #29
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Signed-off-by: Rodney Osodo <socials@rodneyosodo.com>
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Run Update PCB from Schematic; C18 and L3 exist in the schematic but are missing from the layout. |
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Populate C18 with 0R instead of DNP, because a depopulated series part breaks the GNSS feed entirely. |
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Move SIM7080G_DCD off J2 pin 5, which lands on the base board's shared SCL line. |
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Set the DNP attribute and clear the JLCPCB part number on C7, C9 and C10 before fabrication. |
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Restore the ground stitching vias, since this PR drops GND vias from sixty-one to seven. |
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Pour ground on an inner layer, so the RF feeds reference ground rather than the In1 +3V3 plane. |
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Keep RF_ANT and GNSS_ANT on the top layer, since both currently drop to In2.Cu through vias. |
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Recalculate the antenna trace width for 50R, because 0.5mm over this 0.1mm prepreg is roughly 26R. |
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Move C15, C16 and C17 beside U2's VBAT pins; they currently sit ten to fifteen millimetres away. |
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Add netclass patterns for RF_50R and VBAT_HIGH, which are defined but currently match no nets. |
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Restore the silk_over_copper and starved_thermal DRC severities rather than setting both to ignore. |
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Give U2's USB_BOOT a defined level, because JP1 ships open and leaves the pin floating. |
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Bias or close JP2 and JP3, since U2's UART1_RTS input is otherwise left undefined. |
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Add a fuse or current limit to the GNSS bias, since 0805 R3 cannot survive one watt. |
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Place D8 beside U3, because ESD clamping degrades over the present fifteen millimetre run to the connector. |
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Add a bulk capacitor on SIM_VDD next to U3, where C6's 0.1uF is the only decoupling. |
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Add test points on GND, +3V3 and VBAT, as TP1 through TP5 cover only +1V8 and USB. |
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Regenerate the jlcpcb gerbers, BOM and CPL, which still describe the July board rather than this revision. |
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Re-export schematic.pdf, which still shows C7, C9 and C10 as 22pF and D3 instead of D8. |
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Bump the title block revision and date, since v0.5.0 no longer describes this substantially changed schematic. |
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Strip C48677.kicad_sym to ESDA6V1W5, since it also ships ESP32-C6, E07-400M10S and four unrelated connector symbols. |
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Extend the C48677 courtyard to enclose its pads, which sit entirely outside the current 0.65mm outline. |
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Repoint the C48677 3D model at the committed C48677.step, because the EASYEDA2KICAD variable will not resolve. |
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Confirm the KiCad 10 format bump is intended, since every other board here still targets 9.0. |
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Give U1 a JLCPCB field and align D8 and U3, which use 'LCSC Part' instead. |
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Fix the two hole clearance errors on the +1V8 via at 112.0, 91.7, currently 0.00mm against 0.15mm. |
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Move the GND teardrop out of J4's keepout area, which DRC reports as an items-not-allowed error. |
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Restoring silk_over_copper and starved_thermal reveals seven and eleven hidden violations, so fix those rather than ignoring. |
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Commit an fp-lib-table so the modules library resolves, because DRC cannot currently check U2, U3 or D8. |
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Assign real pin types in the C48677 symbol, since its Unspecified pins add five ERC pin_to_pin warnings. |
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Add PWR_FLAGs or correct the VDD_EXT and SIM_VDD pin types, which ERC errors as undriven rails. |
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Have you included tests for your changes?
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Notes