Multi-Layer Offload #1489

auphelia · 2025-11-25T12:14:14Z

TBD

…re/loop_op

Add loop_control and loop_control_wrapper

…gnment

…ion with Vivado

…ased on a lambda filter, updated the loop test to reflect the changes

Extended adjacency_list utility function to accept a lambda for filtering decisions.

…op_op

Update loop tb

…4 mismatch issue)

… an MLO sim is being performed.

Refactor Loop Op flow

… when extracting folding config json

…s not available

preusser

This is looking good functionally.
Please, fix licenses and clean up module interfaces though.

preusser · 2025-12-10T06:18:52Z

finn-rtllib/mlo/cdma/cdma_top.sv

@@ -0,0 +1,452 @@
+// Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file is subject to the Xilinx Design License Agreement located


Please, put this AMD code under the same BSD license as the rest of the project.

preusser · 2025-12-10T06:27:12Z

finn-rtllib/mlo/cdma/cdma_top.sv

+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+
+module cdma_top #(
+    parameter integer                   BURST_LEN = 16,


Please, review the declaration of generics:

Avoid the obsolete parameter keyword for numeric parameters.

Be as restrictive as possible with the integer datatype: bit for binary 0/1 choice, int unsigned for unsigned parameters, and int for values that cannot remain unknown.

Avoid default values for everything that requires a conscious user choice. Only specify defaults when deviations are clear exceptions from a natural intuitive default choice.

preusser · 2025-12-10T06:30:24Z

finn-rtllib/mlo/cdma/cdma_top.sv

+    AXI4SF.master                       m_axis_ddr
+);
+
+if(CDMA_TYPE == 0) begin


Prefer a unique case(CDMA_TYPE) construct with a default case producing an appropriate error message for unsupported values.

preusser · 2025-12-10T06:36:43Z

finn-rtllib/mlo/cdma/krnl_counter.sv

@@ -0,0 +1,107 @@
+`timescale 1ns / 1ps


Don't use module-specific timescales. Rather, specify delays with units at the sites of use.

preusser · 2025-12-10T06:37:21Z

finn-rtllib/mlo/cdma/krnl_counter.sv

@@ -0,0 +1,107 @@
+`timescale 1ns / 1ps
+
+// /*******************************************************************************


Update to appropriate AMD copyright as used in FINN.

preusser · 2025-12-10T07:46:02Z

finn-rtllib/mlo/inst_ip.tcl

@@ -0,0 +1,194 @@
+# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
+#
+# This file is subject to the Xilinx Design License Agreement located


Please, update for use in FINN.

preusser · 2025-12-10T07:48:10Z

finn-rtllib/mlo/local_weight_buffer.sv

@@ -0,0 +1,312 @@
+// Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file is subject to the Xilinx Design License Agreement located


Please, update for the use in FINN.

preusser · 2025-12-10T07:49:13Z

finn-rtllib/mlo/local_weight_buffer.sv

+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+
+module local_weight_buffer #(
+    parameter int unsigned              PE,


Avoid parameter.

preusser · 2025-12-10T07:51:01Z

finn-rtllib/mlo/loop_control.sv

@@ -0,0 +1,277 @@
+    // Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
+    //
+    // This file is subject to the Xilinx Design License Agreement located


Please, update for the use in FINN.

preusser · 2025-12-10T07:52:16Z

finn-rtllib/mlo/loop_control.sv

+
+    module loop_control #(
+        // COMPILER SET, this is the size of the global in, global out frames
+        parameter int unsigned FM_SIZE,


Please, avoid parameter.

Joshua Monson and others added 30 commits June 23, 2025 20:57

remove import iwTypes package

c0c06b2

add CMDA_X IP

9681f18

CDMA generation and import fixes

5661c77

Merge branch 'feature/loop_op' of github.com:jsmonson/finn into featu…

3d02cfd

…re/loop_op

Reorg RTL directories, add line continuation

e5cd116

add forgotten file

5850e63

Merge pull request #1367 from jsmonson/feature/loop_op

1cc3feb

Add loop_control and loop_control_wrapper

[FINNLoop] Update ipi stitching script and fix fetch weights clk assi…

9da9b56

…gnment

[FINNLoop] Saving bd design before validation to allow for investigat…

6272ea4

…ion with Vivado

Merge branch 'feature/finnxsi_integration' into feature/loop_op

51ef902

[FINNLoop] Adding exp cycles function from @jsmonson

b022ca5

move template replacement into mlo_max_iter if-statement

7653487

added the ability to create an adjacency_list of the original model b…

ad8e6ce

…ased on a lambda filter, updated the loop test to reflect the changes

[FINNLoop] Exposing clk and rst signals

6abc5b4

Merge pull request #1376 from Xilinx/feature/adj_list_lambda

761adfa

Extended adjacency_list utility function to accept a lambda for filtering decisions.

Fix continuous combinatorial assignments.

ea1b238

Fixes in serving of memory image.

80ee883

Merge remote-tracking branch 'origin/feature/loop_op' into feature/lo…

cdc6022

…op_op

[FINNLoop] Linting

24c8413

[FINNLoop] Update stitching script to connect components

52cb964

[FINNLoop] Update stitching to expose interfaces

b3329fc

[FINNLoop] Add verilog and system verilog files from rtllib

f063a8a

relocated and reorganize files, fix typo, add missing sources

212d30a

add a branching node and a dyn_matmul to testbench

cb05624

relocated and reorganize files, fix typo, add missing sources

708b49b

Merge pull request #1378 from jsmonson/feature/updated_loop_tb

a6763fb

Update loop tb

[Tests] Add duplicate streams to new loop test

1bade7d

[Tests] Add name for dup strms layer and run cppsim steps

305bc62

[Tests] Add fifo node attribute

ff64113

Adding a test that makes a stitchedIP of the loop body

26646ca

auphelia and others added 25 commits October 23, 2025 18:21

[FINNLoop] Add fifo sizing to upper level and update ip stitching

cbd6de2

[FINNLoop] Move tcl cmds into template

5c7961c

[BuildSteps] Update build flow with refactored loop op integration

e7d2b5a

[Tests] Add end2end builder test for mlo

0417723

Merge branch 'feature/loop_op' into feature/refactor_loop_ipgen

67f90d1

[LoopRolling] Use hierarchy_list as a list of lists

b3bb82e

update loop_hierarhcy in builder and checking in LoopExtraction

469310f

[MLO INT4] Disable narrow weights when MLO is being used (fix for INT…

9ad2da6

…4 mismatch issue)

add fix for rhs_style

29f477b

[MLO] Clean-up files after cherry-picking commits

1c3a0ff

[MLOSim VerifyStep] Fixing issue when user request a full context and…

589fb30

… an MLO sim is being performed.

[Builder] Remove f in print statement

7a546cc

[MLO] Insert GiveUniqueNodeNames

be2310c

Merge pull request #1466 from Xilinx/feature/refactor_loop_ipgen

7cc5ee2

Refactor Loop Op flow

[MLO] Make sure that body is saved after changes

0b82ff3

[MLO] Refactor node naming for loop node

4944870

Merge branch 'dev' into feature/loop_op

583d40c

[Tests] Thresholding: move sim reset into prehook fct

462fddd

[FINNLoop] Update exp cycles estimate

18423d1

[MLO] Make sure subgraph nodes are named differently from upper level…

bb4ae3d

… when extracting folding config json

Merge branch 'dev' into feature/loop_op

39e3eff

[FINNLoop] Propagate rtlsim trace node attribute to execute node

520ea98

[MLO] Cleanup and align with recent changes

769d6af

[Deps] Make import of finn xsi optional in case Vivado installation i…

fbc2afe

…s not available

[Tests] Add markers to finnloop test

5da9d6b

auphelia requested a review from preusser November 25, 2025 15:57

auphelia marked this pull request as ready for review November 25, 2025 15:58

preusser requested changes Dec 10, 2025

View reviewed changes

auphelia added 2 commits December 10, 2025 09:42

Merge branch 'dev' into feature/loop_op

a2f6327

Merge branch 'dev' into feature/loop_op

5cc6d48

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Multi-Layer Offload #1489

Multi-Layer Offload #1489

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		@@ -0,0 +1,107 @@
		`timescale 1ns / 1ps

		// /*******************************************************************************

Multi-Layer Offload #1489

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Multi-Layer Offload #1489

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