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Pull requests: Xilinx/PYNQ-Metadata

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Pull requests list

Skipping signal polarity checks when connecting to monitor IP type.
#19 opened Apr 25, 2024 by STFleming Collaborator Loading…
Fix for Issue #14 HwhFrontend doesn't add Registers for AXI_FULL ports
#17 opened Nov 28, 2023 by STFleming Collaborator Loading…
1
@STFleming
Reducing strictness on Memrange parsing
#16 opened Nov 28, 2023 by STFleming Collaborator Loading…
@STFleming
ProTip! no:milestone will show everything without a milestone.