[npu/ttx] feat: add DeepSeekV4 hc_post operator on Triton

[lyujheng]

Summary

Add the DeepSeekV4 hc_post (Head Combination Post-processing) operator with Triton NPU kernel implementation.

Changes

• Kernel: mojo_opset/backends/ttx/kernels/npu/hc_post.py — Triton kernel for fused head combination post-processing (post * x + comb @ residual)
• Operator: mojo_opset/core/operators/hc_post.py — MojoHcPost operator with torch reference implementation
• Backend: mojo_opset/backends/ttx/operators/hc_post.py — TTX backend binding
• Compile: register_fake + custom_op registration for torch.compile(fullgraph=True)
• Tests: accuracy, performance, and compile (opcheck + fullgraph) tests

Performance (Device Latency, 910B, HC=4, dtype=bf16)

AscendC baseline from branch tongbowen/dpskv4_ascend

Shape (B, S, HC, D)	Triton-Ascend	AscendC	Speedup
(1, 16, 4, 4096)	6.90 us	7.83 us	1.13x
(1, 16, 4, 7168)	10.64 us	11.00 us	1.03x
(32, 16, 4, 4096)	45.92 us	54.26 us	1.18x
(32, 16, 4, 7168)	95.66 us	95.11 us	0.99x
(64, 16, 4, 4096)	85.68 us	102.19 us	1.19x
(64, 16, 4, 7168)	201.17 us	189.51 us	0.94x

Accuracy (bf16, HC=4, atol=5e-3, rtol=5e-3)

Shape (B, S, HC, D)	Result
(1, 16, 4, 4096)	✅ PASS
(1, 16, 4, 7168)	✅ PASS
(4, 4, 4, 4096)	✅ PASS
(4, 4, 4, 7168)	✅ PASS
(8, 16, 4, 4096)	✅ PASS
(8, 16, 4, 7168)	✅ PASS

[gemini-code-assist]

Code Review

This pull request introduces the hc_post operator to the Mojo opset, including its NPU backend Triton kernel implementation, registration as a PyTorch custom operator, and corresponding accuracy, performance, and graph compilation tests. A critical issue was identified in the Triton kernel where the use of tl.extract_slice will cause compilation failures on Ascend NPUs. It is recommended to use tl.static_range to unroll the loop and perform standard slicing instead.

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