Feature/avalon#37

Merged

Paebbels merged 13 commits intoVHDL:mainfrom

parhamsoltani:feature/avalon

Jan 12, 2026

Commits on Dec 10, 2025

Refactor Wishbone and Avalon interfaces to use spec-compliant signal names with VHDL-2019 bit types
parhamsoltani
committed
minor change on compileorder
parhamsoltani
committed

Commits on Dec 11, 2025

updated wishbone using std_ulogic/std_ulogic_vector, and unsigned types with UpperCamelCase naming
parhamsoltani
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updated avalon using std_ulogic/std_ulogic_vector, and unsigned types with UpperCamelCase naming
parhamsoltani
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Revert "updated wishbone using std_ulogic/std_ulogic_vector, and unsigned types with UpperCamelCase naming"
parhamsoltani
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This reverts commit d05a9dfa1dbeca6c137467a2c9827fd5d0d6045a.
parhamsoltani
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Clean Avalon interface only (restored for separate PR, including recent updates)
parhamsoltani
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linebreaks added
parhamsoltani
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Merge branch 'feature/avalon' of https://github.com/parhamsoltani/Interfaces into feature/avalon
parhamsoltani
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linebreak added
parhamsoltani
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linebreaker added
parhamsoltani
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Commits on Dec 14, 2025

Apply suggestions from code review

parhamsoltani
and
Paebbels
authored

Commits on Jan 6, 2026

Add Avalon-MM and Avalon-ST Minimal interface packages
parhamsoltani
committed