Diagrams

RISC-V Project Diagrams

This page displays the schematics of each module in the RISC-V multi-cycle CPU system. All blue wires are ports that other modules connect to, while black wires are internal signals. Unless otherwise stated, all wires are one bit in width.

Table of Contents

1. Top-Level Module
2. Arithmetic Logic Unit (ALU)
3. Fetch
4. Instruction Decoder
5. ALU Decoder
6. Register File
7. Control Finite State Machine (Control FSM)
8. Memory
9. Memory Loader

Top-Level Module

Arithmetic Logic Unit (ALU)

Fetch

Instruction Decoder

ALU Decoder

Register File

Control Finite State Machine (Control FSM)

Memory

Memory Loader