Track fitter resource utilization by entity

[TheDeepestSpace]

This adds fitter resource utilization by entity metric from the fitter report for #216

[github-actions]

🔧 DE1-SoC Synthesis Report Summary Diff

📊 Fitter Summary (.fit.summary)

No baseline available from main branch

View PR synthesis results

Fitter Status : Successful - Thu Apr  2 04:03:01 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : utoss-risc-v
Top-level Entity Name : top
Family : Cyclone V
Device : 5CSEMA5F31C6
Timing Models : Final
Logic utilization (in ALMs) : 1,427 / 32,070 ( 4 % )
Total registers : 1262
Total pins : 15 / 457 ( 3 % )
Total virtual pins : 0
Total block memory bits : 16,384 / 4,065,280 ( < 1 % )
Total RAM Blocks : 4 / 397 ( 1 % )
Total DSP Blocks : 0 / 87 ( 0 % )
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )

🔢 Fitter Resource Utilization by Entity

No baseline available from main branch

View PR synthesis results

Compilation Hierarchy Node                     ALMs needed [=A-B+C]  [A] ALMs used in final placement  [B] Estimate of ALMs recoverable by dense packing  [C] Estimate of ALMs unavailable  ALMs used for memory  Combinational ALUTs  Dedicated Logic Registers  I/O Registers  Block Memory Bits  M10Ks  DSP Blocks  Pins  Virtual Pins  Full Hierarchy Name                                                                    Entity Name         Library Name
|top                                           1427.0 (0.5)          1586.5 (0.5)                      177.0 (0.0)                                        17.5 (0.0)                        0.0 (0.0)             1747 (1)             1262 (0)                   0 (0)          16384              4      0           15    0             |top                                                                                   top                 work
   |memory_map:memory_map|                     37.8 (37.8)           41.8 (41.8)                       4.3 (4.3)                                          0.3 (0.3)                         0.0 (0.0)             67 (67)              12 (12)                    0 (0)          16384              4      0           0     0             |top|memory_map:memory_map                                                             memory_map          work
      |altsyncram:M0_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0                                         altsyncram          work
         |altsyncram_9hp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0|altsyncram_9hp1:auto_generated          altsyncram_9hp1     work
      |altsyncram:M1_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0                                         altsyncram          work
         |altsyncram_ahp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0|altsyncram_ahp1:auto_generated          altsyncram_ahp1     work
      |altsyncram:M2_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0                                         altsyncram          work
         |altsyncram_bhp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0|altsyncram_bhp1:auto_generated          altsyncram_bhp1     work
      |altsyncram:M3_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0                                         altsyncram          work
         |altsyncram_chp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0|altsyncram_chp1:auto_generated          altsyncram_chp1     work
   |utoss_riscv:core|                          1388.6 (131.9)        1544.2 (143.3)                    172.7 (15.3)                                       17.2 (4.0)                        0.0 (0.0)             1679 (163)           1250 (177)                 0 (0)          0                  0      0           0     0             |top|utoss_riscv:core                                                                  utoss_riscv         work
      |ALU:alu|                                372.3 (372.3)         386.2 (386.2)                     19.8 (19.8)                                        5.9 (5.9)                         0.0 (0.0)             521 (521)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|ALU:alu                                                          ALU                 work
      |ControlFSM:control_fsm|                 31.8 (31.8)           32.2 (32.2)                       0.5 (0.5)                                          0.1 (0.1)                         0.0 (0.0)             49 (49)              17 (17)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|ControlFSM:control_fsm                                           ControlFSM          work
      |Instruction_Decode:instruction_decode|  57.0 (48.8)           57.0 (48.7)                       0.2 (0.0)                                          0.1 (0.1)                         0.0 (0.0)             108 (96)             0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Instruction_Decode:instruction_decode                            Instruction_Decode  work
         |ALUdecoder:instanceALUDec|           7.2 (7.2)             8.3 (8.3)                         1.2 (1.2)                                          0.0 (0.0)                         0.0 (0.0)             12 (12)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec  ALUdecoder          work
      |MemoryLoader:MemLoad|                   30.1 (30.1)           28.3 (28.3)                       0.1 (0.1)                                          2.0 (2.0)                         0.0 (0.0)             64 (64)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|MemoryLoader:MemLoad                                             MemoryLoader        work
      |fetch:fetch|                            72.8 (72.8)           72.8 (72.8)                       0.5 (0.5)                                          0.5 (0.5)                         0.0 (0.0)             95 (95)              64 (64)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|fetch:fetch                                                      fetch               work
      |registerFile:RegFile|                   692.7 (692.7)         824.5 (824.5)                     136.3 (136.3)                                      4.6 (4.6)                         0.0 (0.0)             679 (679)            992 (992)                  0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|registerFile:RegFile                                             registerFile        work

⏱️ Timing Analysis Summary (.sta.summary)

No baseline available from main branch

View PR synthesis results

------------------------------------------------------------
Timing Analyzer Summary
------------------------------------------------------------

Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
Slack : 4.839
TNS   : 0.000

Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.375
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.876
TNS   : 0.000

Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
Slack : 5.002
TNS   : 0.000

Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
Slack : 0.388
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.830
TNS   : 0.000

Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
Slack : 10.876
TNS   : 0.000

Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.181
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.786
TNS   : 0.000

Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
Slack : 11.803
TNS   : 0.000

Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
Slack : 0.171
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.778
TNS   : 0.000

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Comparing synthesis results from main branch vs. this PR