Address verilator warnings

Makefile

@@ -18,8 +18,7 @@ RISCOF_CONFIG        := $(RISCOF_DIR)/config.ini
 # ===========================
 # Verilator flags
 # ===========================
-VERILATOR_FLAGS := -Wall --binary --trace --timing -sv -cc \
-	-O3 -Wno-fatal
+VERILATOR_FLAGS := -Wall --binary --trace --timing -sv -cc -O3
 
 # Testbench-only defines
 TB_DEFINES := -DTESTBENCH

envs/simulation/MA.sv

@@ -23,10 +23,10 @@ module MA #( parameter SIZE = 1024 )
   always @(posedge clk) begin
     read_data <= M[address[31:2]]; // 2 LSBs used for byte addressing
 
-    if (write_enable[0]) M[address[31:2]][7:0]   <= write_data[7:0];
-    if (write_enable[1]) M[address[31:2]][15:8]  <= write_data[15:8];
-    if (write_enable[2]) M[address[31:2]][23:16] <= write_data[23:16];
-    if (write_enable[3]) M[address[31:2]][31:24] <= write_data[31:24];
+    if (write_enable[0]) M[address[11:2]][7:0]   <= write_data[7:0];
+    if (write_enable[1]) M[address[11:2]][15:8]  <= write_data[15:8];
+    if (write_enable[2]) M[address[11:2]][23:16] <= write_data[23:16];
+    if (write_enable[3]) M[address[11:2]][31:24] <= write_data[31:24];
   end
 
 endmodule

src/Instruction_Decode/MemoryLoader.sv

@@ -85,4 +85,4 @@ module MemoryLoader
                 MemWriteByteAddress = 4'bxxxx;
             end
         endcase
-endmodule
+endmodule

src/utoss_riscv.sv

@@ -206,7 +206,7 @@ module utoss_riscv
   , .imm_ext          ( imm_ext          )
   , .memory_address   ( memory__address  )
   , .memory_data      ( mem_load_result  )
-  , .write_enable     ( memory__write_enable )
+  , .write_enable     ( memory__write_enable[0] )
   , .rd1              ( rd1              )
   , .rd2              ( rd2              )
   , .result           ( result           )