[AMD][MI355X] DSv4 SGLang agentic: v0.5.15 image, router, HiCache#2146

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seungrokj wants to merge 23 commits into

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amd/agentx_dsv4_sgl

Commits on Jul 14, 2026

[AMD][MI355X] Update DSv4 SGLang agentic launcher to v0.5.14 image with router and HiCache support

seungrokj
and
claude
committed
[AMD][MI355X] Add dram-utilization 0.80 to DSv4 SGLang agentic sweep config

seungrokj
and
claude
committed
Update perf-changelog with PR link for DSv4 SGLang agentic entry

seungrokj
and
claude
committed
[AMD][MI355X] Remove --context-length and comment out extra sweep configs for initial validation

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang agentic: use compressed attention, 2x max-running-requests, re-enable all sweep configs

seungrokj
and
claude
committed
[AMD][MI355X] Fix cudaHostRegister OOM: lower hicache-ratio to 4, adjust sweep concurrency

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang agentic: focus sweep on DPA configs, scale concurrency to 96

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang agentic: add non-DPA baseline config (tp=8, conc 1-8)

seungrokj
and
claude
committed
[AMD][MI355X] exclude mia1-p01-g12 from agentic salloc

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang: narrow DPA sweep ranges, add disagg agentic hicache recipe

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang: refactor launcher, rename config key, bump image

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang: fix kv-offload-backend to map syntax, add mori p2p, revert image

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang: remove disagg agentic hicache recipe

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang: add vllm-router and mooncake backend to agentic sweep

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang: bump agentic-hicache image to v0.5.15

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang: update perf-changelog for image bump and drop disagg entry

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang: move PARALLEL_ARGS init before DPA block

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang: revert agentic-hicache image to v0.5.14

seungrokj
and
claude
committed
[AMD][MI355X] DSv4 SGLang: revert mem-fraction-static to 0.90 and chunked-prefill to 8192

seungrokj
and
claude
committed
Merge branch 'main' into amd/agentx_dsv4_sgl
seungrokj
authored
chore(ci): trigger full sweep
cquil11
committed
fix(changelog): append PR entry after main
cquil11
committed
fix(changelog): omit null optional metadata
cquil11
committed

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[AMD][MI355X] DSv4 SGLang agentic: v0.5.15 image, router, HiCache#2146

[AMD][MI355X] DSv4 SGLang agentic: v0.5.15 image, router, HiCache#2146
seungrokj wants to merge 23 commits into
mainfrom
amd/agentx_dsv4_sgl

Commits on Jul 14, 2026

[AMD][MI355X] Update DSv4 SGLang agentic launcher to v0.5.14 image with router and HiCache support

[AMD][MI355X] Add dram-utilization 0.80 to DSv4 SGLang agentic sweep config

Update perf-changelog with PR link for DSv4 SGLang agentic entry

[AMD][MI355X] Remove --context-length and comment out extra sweep configs for initial validation

[AMD][MI355X] DSv4 SGLang agentic: use compressed attention, 2x max-running-requests, re-enable all sweep configs

[AMD][MI355X] Fix cudaHostRegister OOM: lower hicache-ratio to 4, adjust sweep concurrency

[AMD][MI355X] DSv4 SGLang agentic: focus sweep on DPA configs, scale concurrency to 96

[AMD][MI355X] DSv4 SGLang agentic: add non-DPA baseline config (tp=8, conc 1-8)

[AMD][MI355X] exclude mia1-p01-g12 from agentic salloc

[AMD][MI355X] DSv4 SGLang: narrow DPA sweep ranges, add disagg agentic hicache recipe

[AMD][MI355X] DSv4 SGLang: refactor launcher, rename config key, bump image

[AMD][MI355X] DSv4 SGLang: fix kv-offload-backend to map syntax, add mori p2p, revert image

[AMD][MI355X] DSv4 SGLang: remove disagg agentic hicache recipe

[AMD][MI355X] DSv4 SGLang: add vllm-router and mooncake backend to agentic sweep

[AMD][MI355X] DSv4 SGLang: bump agentic-hicache image to v0.5.15

[AMD][MI355X] DSv4 SGLang: update perf-changelog for image bump and drop disagg entry

[AMD][MI355X] DSv4 SGLang: move PARALLEL_ARGS init before DPA block

[AMD][MI355X] DSv4 SGLang: revert agentic-hicache image to v0.5.14

[AMD][MI355X] DSv4 SGLang: revert mem-fraction-static to 0.90 and chunked-prefill to 8192

Merge branch 'main' into amd/agentx_dsv4_sgl

chore(ci): trigger full sweep

fix(changelog): append PR entry after main

fix(changelog): omit null optional metadata