Digital Multiplier Design (VHDL)

A digital design project implementing and comparing hardware multiplier architectures in VHDL, developed as an academic assignment in digital systems design.

Table of Contents

• Overview
• Project Structure
• Array Multiplier
  • Hardware Requirements
  • Characteristics
  • VHDL Implementation
• Add and Shift (Sequential Multiplier)
  • Hardware Requirements
  • VHDL Implementation
• Comparison with Other Algorithms
• Simulation / Usage
• Contribute
• License

Overview

Binary multiplication can be implemented in hardware using several different architectures, each with its own trade-offs between speed, area (gate count), and design complexity. This project implements two of these architectures and documents two additional ones for comparison:

1. Array Multiplier — a combinational, fully-parallel multiplier built from AND gates, half adders, and full adders.
2. Shift and Add (Sequential Multiplier) — a sequential, clock-driven multiplier that computes the product one bit at a time using a shift-and-accumulate FSM.
3. Booth's Algorithm (discussed, not implemented) — handles signed multiplication uniformly and reduces the number of partial-product additions.
4. Wallace Tree (discussed, not implemented) — sums partial products in parallel using carry-save counters to minimize delay.

Project Structure

.
├── Array Multiplier/     # Combinational array multiplier (VHDL source)
├── Add & Shift/          # Sequential shift-and-add multiplier (VHDL source)
└── Digital Project.pdf   # Project report / slides covering all four algorithms

Array Multiplier

A combinational multiplier that computes the product directly from partial products generated by AND gates, then reduces them using a network of half adders and full adders — similar in structure to how multiplication is done by hand (long multiplication), but performed entirely in parallel hardware.

Hardware Requirements (for an n-bit multiplier)

Component	Count
AND gates	n²
Half adders	n
Full adders	n(n − 2)

Characteristics

• Fully combinational — no clock required, output is available after propagation delay.
• Gate count and critical-path delay both grow with n, making it fast but area-expensive for large bit widths.

VHDL Implementation

The Array Multiplier folder contains a structural VHDL implementation using chained half_adder and full_adder components to build up the partial-product reduction network, producing an 8-bit product S from two 4-bit operands.

Add and Shift (Sequential Multiplier)

A sequential multiplier that trades speed for hardware simplicity. On each clock cycle:

1. The least significant bit of the multiplier register is checked.
2. If it is 1, the multiplicand is added to the accumulator.
3. The combined accumulator + multiplier register is then shifted right by one bit.
4. This repeats for all n bits of the multiplier; the final result is held in the accumulator.

Hardware Requirements

• 3 registers (multiplicand, multiplier/accumulator working registers)
• A counter (counts up to n bits after each shift)
• An arithmetic unit (ALU) for addition

VHDL Implementation

The Add & Shift folder contains a generic (N-bit, default 8) sequential multiplier described as a finite state machine with states:

IDLE → LOAD → CHECK_ADD → SHIFT → FINISH

• IDLE: waits for start.
• LOAD: loads operands A and B into working registers, resets the accumulator and counter.
• CHECK_ADD: conditionally adds the multiplicand to the accumulator based on the current LSB.
• SHIFT: performs a logical right shift across the combined accumulator/multiplier register.
• FINISH: asserts done and outputs the final product P.

Entity interface:

Port	Direction	Width	Description
clk	in	1	Clock
reset	in	1	Synchronous reset
start	in	1	Starts a new multiplication
A	in	N	Multiplicand
B	in	N	Multiplier
P	out	2*N	Product
done	out	1	Asserted when result is ready

Comparison with Other Algorithms

Algorithm	Type	Signed Support	Relative Speed	Relative Area
Array Multiplier	Combinational	No (unsigned)	Fast	Large (O(n²) gates)
Add and Shift	Sequential	No (unsigned)	Slow (n cycles)	Small
Booth's Algorithm	Combinational/Sequential	Yes	Faster than plain shift-and-add	Moderate
Wallace Tree	Combinational (carry-save)	No	Fastest	Large

• Booth's Algorithm computes the product identically for signed and unsigned operands and reduces the number of partial-product additions needed.
• Wallace Tree sums partial-product bits column-by-column in parallel using counters, avoiding sequential carry propagation and minimizing delay at the cost of extra area.

Simulation / Usage

Each folder contains synthesizable VHDL source files intended for simulation in a standard HDL simulator (e.g., ModelSim, GHDL, or Vivado Simulator):

1. Open the project in your simulator of choice.
2. Compile all VHDL files within the relevant folder (Array Multiplier or Add & Shift).
3. For the Array Multiplier, apply the two input operands and observe the product output combinationally.
4. For the Add & Shift multiplier, instantiate sequential_multiplier, drive clk/reset, apply A and B, pulse start, and wait for done before reading P.
5. A testbench is expected/recommended for each design to automate stimulus and result checking.

Note: Some VHDL snippets in the source material contain OCR/transcription artifacts (e.g. stray characters, malformed signal names). Review and clean up the source files before compiling.

Contribute

Contributions are welcome and greatly appreciated!

Whether you'd like to fix a bug, improve documentation, optimize code, or add a new embedded systems project, your help is appreciated. you can also reach out via email at rseyednozadi@gmail.com. If you'd like to improve this project:

1. Fork the repository.
2. Create a feature branch (git checkout -b feature/booth-multiplier).
3. Make your changes (e.g. fix VHDL syntax issues, add a testbench, implement Booth's or Wallace Tree).
4. Commit your changes with a clear message.
5. Open a pull request describing what you changed and why.

License

This project is licensed under the MIT License. See the LICENSE file for details.