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Add support for ext dispatch packet 4. - #8401

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Add support for ext dispatch packet 4.#8401
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❌ PR Check — Action Required

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📝 PR Title/Description ❌ Fail Error: PR description must reference a JIRA ID, ISSUE ID, or a GitHub closing keyword.
Expected: include a JIRA ID / ISSUE ID line (separator : or -, or omitted; value may be a JIRA key, a number with/without #, or a link), OR a closing keyword + issue reference. Accepted examples:
JIRA ID : TESTAUTO-6039
JIRA ID - #330
JIRA ID #330
JIRA ID (on separate line)
ROCM-25757
ISSUE ID : TESTUTO-3334
ISSUE ID #3334
ISSUE ID - TESTAUTO-3433
ISSUE ID (on separate line)
AIRUNTIME-2352
ISSUE ID : https://github.com/<org_name>/<repo_name>/issues/1234
Closes #10
Fixes octo-org/octo-repo#100
Resolves: #123
#123
https://github.com/<org_name>/<repo_name>/issues/123
Current: no valid JIRA/ISSUE/closing-keyword reference found
Forbidden Files ✅ Pass
🧪 Unit Test ❌ Fail Error: Source/code files changed without an accompanying unit test.
Expected: add at least one test file named like test_<name>.py / test_<name>.cpp (or <name>_test.*).
Current: code file(s) changed: projects/clr/rocclr/device/rocm/rocdevice.cpp, projects/clr/rocclr/device/rocm/rocsettings.cpp, projects/clr/rocclr/device/rocm/rocsettings.hpp, projects/clr/rocclr/device/rocm/rocvirtual.cpp, projects/clr/rocclr/device/rocm/rocvirtual.hpp (+1 more); no test file found
🔎 pre-commit ⏳ Pending ⏳ Still running…
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🚫 Please fix the failed policies before requesting reviews.

The following policy checks failed:

  • ❌ PR Title/Description
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The Not ready to Review label has been added to this PR.
Once all policies pass, the label will be removed automatically.

@cfreeamd cfreeamd left a comment

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🤖 AI-assisted pre-review (for @cfreeamd)

Only reviewing the rocr-runtime file (hsa_ext_amd.h). The change is ABI-safe: amd_launch_descriptor_t resolves via the existing #include "amd_launch_descriptor.h", both new unions preserve the original field sizes/offsets (1 byte and 8 bytes on LP64), the 64-byte packet size is unchanged, and existing .setup/.dep_signal accesses still compile through the anonymous unions. Two non-blocking notes inline.

uint8_t setup; // Format 3: full 8-bit setup field
struct { // Format 4: bitfield with dispatch_ahead
uint8_t setup_dimensions : 2;
uint8_t dispatch_ahead_programmatic : 1;

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🤖 AI-assisted pre-review (for @cfreeamd)

[Optional] This setup byte is read by the CP/FW, so its bit layout is part of the hardware contract — but C bitfield allocation order is implementation-defined. It matches the documented layout (dimensions bits[1:0], dispatch_ahead_programmatic bit[2]) only on little-endian GCC/Clang, which is all AMD ships, yet the rest of HSA deliberately encodes such fields with explicit shift/mask constants (e.g. HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS) rather than bitfields. Consider a mask/shift accessor or a static_assert locking the layout. Note too that the anonymous struct/union requires C11+ from every consumer of this public header.

Comment thread projects/rocr-runtime/runtime/hsa-runtime/inc/hsa_ext_amd.h
@kjayapra-amd
kjayapra-amd force-pushed the users/kjayapra/packet4temp branch 4 times, most recently from db1dd4c to 8009b98 Compare July 14, 2026 01:53
Comment thread projects/rocr-runtime/runtime/hsa-runtime/inc/hsa_ext_amd.h Outdated
@kjayapra-amd
kjayapra-amd force-pushed the users/kjayapra/packet4temp branch 2 times, most recently from 274a13c to c0fb5a0 Compare July 14, 2026 18:23

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Did we miss a spot here?

@@ -1539,7 +1567,8 @@ bool VirtualGPU::dispatchAqlPacket(AqlPacket* packet, uint16_t header,
}
return true;
} else {
dispatchBlockingWait(reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet));
hsa_amd_packet_type8_t amd_format = static_cast<hsa_amd_packet_type8_t>(rest & 0xFF);

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This is a bug, you cannot do this for a regular packet., this needs a ext packet detect guard. rest && 0xff will give you dimensions for a regular packet. for a dim3 kenrel it means we think now its type3

@kjayapra-amd
kjayapra-amd force-pushed the users/kjayapra/packet4temp branch from c0fb5a0 to 4d9adf1 Compare July 16, 2026 16:52

@saleelk saleelk left a comment

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its mising the change in queue.h

bool __forceinline isExtDispatch() const {
return (type(packet.header) == HSA_PACKET_TYPE_VENDOR_SPECIFIC &&
amd_vendor.format == HSA_AMD_PACKET_TYPE_EXT_KERNEL_DISPATCH);
}

@@ -1419,6 +1424,24 @@ bool VirtualGPU::dispatchGenericAqlPacket(AqlPacket* packet, uint16_t header, ui
*aql_loc = *packet;

metadata_preloader_.Set(packet, header, index & queueMask);

// For Format 4 (DISPATCH1), set the launch_descriptor pointer in the AQL packet

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this could be done inside the Set function btw . Also fix the comment

Comment thread projects/clr/rocclr/device/rocm/rocvirtual.cpp
@kjayapra-amd
kjayapra-amd force-pushed the users/kjayapra/packet4temp branch 3 times, most recently from bfd67c5 to 45bc161 Compare July 21, 2026 19:17
@kjayapra-amd
kjayapra-amd force-pushed the users/kjayapra/packet4temp branch from 45bc161 to afbd91b Compare July 28, 2026 19:46
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3 participants