CSA compressor: review-response fixups for the ratio=128 kernels (follow-up to #427) - #452
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…ister probe fn.artifacts is nvidia-cutlass-dsl's internal JitFunctionArtifacts dataclass; the documented accessor on the compiled handle is the __ptx__ property (JitCompiledFunction), which is None when PTX retention (CUTE_DSL_KEEP=ptx) is off instead of poisoning ptxas input. Skip kernels that expose no PTX with a clear message and exit nonzero (nothing was verified for them). Signed-off-by: zky <kaiyue.zhou@z.ai>
…backward The backward loaded each row's grad_out vec twice (phases 2 and 4, an L1-resident reload). Loading it once in phase 2 and holding the register vec across the phase barriers is now a per-bucket schedule field (goreuse), decided by measured pure-kernel time (interleaved same-process A/B on one B200, median-100/warmup-30, nsys per-launch, reproduced order-swapped; ptxas spill is the only veto, and no schedule spills — sm_100a 0 spill / 0 stack everywhere): bwd bucket shape base -> reuse delta decision c1d128 small 1x8192 8.45 -> 6.27 us +25.8% adopt c1d128 small 3x8192 16.10 -> 11.68 +27.4% adopt c1d128 default 1x131072 63.87 -> 64.70 -1.3% keep reload c2d128 small 1x8192 11.30 -> 10.66 +5.7% adopt c2d128 default 1x65536 61.25 -> 60.32 +1.5% adopt c1d512 default 1x8192 17.65 -> 17.28 +2.1% adopt (65536: +0.2%) c2d512 default 1x8192 28.27 -> 27.84 +1.5% adopt (65536: -0.1%) The small-bucket wins land despite 48 -> 64 (c1d128) / 77 -> 78 (c2d128) registers: those grids underfill the machine, so register residency is not the binding constraint. The c1d128 default keeps the baseline phase-4 reload (goreuse=False compiles to byte-identical PTX vs the pre-change kernel). dKV/dScore are bitwise-identical with and without the field on every schedule (same read-only values move into registers; verified per shape), dAPE A/B delta sits at within-variant replay-noise scale. Contract gate PASS 21/21 (3-run determinism, tolerance, fp64 parity, schedule coverage fwd 10/10 bwd 6/6); pytest -m 'L0 or L1' fe_api/csa/test_CSA_compressor.py: 98 passed, 1 skipped. Docs tables re-measured on the docs' own bases for the two rows that moved outside session noise; long-context rows measured within noise of their published cells and stand. Signed-off-by: zky <kaiyue.zhou@z.ai>
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No actionable comments were generated in the recent review. 🎉 ℹ️ Recent review info⚙️ Run configurationConfiguration used: Path: .coderabbit.yaml Review profile: CHILL Plan: Enterprise Run ID: 📒 Files selected for processing (4)
📝 WalkthroughWalkthroughThe ratio-128 CSA backward kernel adds a ChangesRatio-128 CSA updates
Estimated code review effort: 3 (Moderate) | ~25 minutes Sequence Diagram(s)sequenceDiagram
participant Schedule as _bwd_schedule_r128
participant Launch as _compressor_bwd_r128_launch
participant Kernel as _compressor_bwd_r128_kernel
participant GradOut as mGO
Schedule->>Launch: select goreuse
Launch->>Kernel: pass compile-time goreuse
Kernel->>GradOut: load grad_out
Kernel->>Kernel: reuse fr_go when goreuse is enabled
Kernel->>GradOut: reload grad_out when goreuse is disabled
Suggested labels: 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches🧪 Generate unit tests (beta)
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Anerudhan
approved these changes
Aug 3, 2026
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Thanks @zkyue for the request. Launching the CI for the PR. |
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@cudnn-ci-bot run |
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🚀 Running mirror pipeline Branch: cudnn-gh/pr-452-037a53b |
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What
Two review-response fixups from the CodeRabbit round on #427 that were ready on the
review branch but missed the merge window (#427 merged at head d77e48e). Both were
built on exactly that head; the cherry-pick onto
develop(b950af1) is clean and theCSA files are byte-identical to the reviewed pre-merge state, except a one-line
stale-comment fix in the test file (flagged in review; no functional change).
678fca3f— bench(csa): use the DSL's documented__ptx__accessor in the r128register probe.
fn.artifactsis nvidia-cutlass-dsl's internalJitFunctionArtifactsdataclass; the documented accessor on the compiled handle isthe
__ptx__property (JitCompiledFunction), which isNonewhen PTX retention(
CUTE_DSL_KEEP=ptx) is off instead of poisoning ptxas input. Kernels that exposeno PTX are now skipped with a clear message and a nonzero exit (a kernel that
wasn't probed wasn't verified). Verified against nvidia-cutlass-dsl 4.6.1;
identical 16-kernel table, ALL 0 spill / 0 stack.
037a53ba— CSA compressor: adopt per-bucket grad_out register reuse in the r128backward. The backward loaded each row's grad_out vec twice (phases 2 and 4).
Loading it once and holding the register vec across the phase barriers is now a
per-bucket schedule field (
goreuse), decided by measured time and adopted in5 of 6 backward buckets; the one measured loser (c1d128 default) keeps the
reload and compiles to byte-identical PTX vs the pre-change kernel. dKV/dScore are
bitwise-identical with and without the field on every schedule; no schedule spills
either way (0 spill / 0 stack, sm_100a).
Performance (goreuse commit)
Methodology: nsys pure-kernel per-launch durations (kernel time only — no wrapper,
launch, or sync overhead), median of 100 after 30 warmup; both variants interleaved
in one process on the same clocks and the same input tensors; reproduced
order-swapped. One B200. Measured on the review branch at e70f6140, whose CSA files
are byte-identical to this branch apart from the one-line test-comment fix, and the
adopted buckets compile to byte-identical PTX vs the measured kernels — byte-identical
PTX means the measured kernels are the shipped kernels (absolute timings vary within
the session-noise envelope below).
Docs tables updated for the two configurations (both tables) that moved outside
session noise (c1d128 8192: bwd 8.4 → 6.3 µs; c2d128 8192: 11.2 → 10.5 µs
kernel-time); long-context rows measured within the ±3% session-noise envelope of
their published cells and stand.
Responds to CodeRabbit feedback on #427
fn.artifacts.PTXis a non-public surface) → fixed in678fca3fas described above.
adopted where it wins,
037a53ba. The register table was a poor predictor: thebucket with the largest growth (c1d128 small, 48 → 64 regs) wins the most because
its small grid underfills the machine, while the one loser has unchanged registers
(80 → 80).
no code change; the duplication is deliberate and staked in the gate's docstring.
The gate is the PR's numerics authority, so its reference should be auditable in
place rather than imported across
benchmark/↔test/python(neither is apackage; conftest import-order constraints). Drift is checked, not trusted: every
gate run first cross-checks the copied reference against the shipped production
ratio=4 backward (bitwise dKV/dScore,
validate_reference()) and fails beforegating anything if the copy has drifted.
Validation (re-run on this branch,
develop+ these 2 commits, B200, 2026-07-30)eager, fp64-oracle parity, overflow NaN-pattern case; schedule coverage fwd 10/10,
bwd 6/6 asserted through the dispatch tables, including the goreuse fields).
-m "L0 or L1" fe_api/csa/test_CSA_compressor.py: 98 passed, 1 skipped.__ptx__path): 16 kernels probed (sm_100a);ALL 0 spill / 0 stack.
Summary by CodeRabbit
New Features
Documentation
Bug Fixes