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[Commo] Optimize grouped MXFP8 requantization - #3560
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Oleg-Goncharov wants to merge 26 commits into
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Oleg-Goncharov wants to merge 26 commits into
Oleg-Goncharov wants to merge 26 commits into
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Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
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Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
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@Oleg-Goncharov This PR seems to have some unrelated changes (like the nccl ep submodule). Could you fix that? |
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Adapt the cuDNN warp-specialized BF16 kernel to compact input scales, E4M3/E5M2 input, TE output layouts, optional rowwise scale swizzling, and device-side grouped offsets. Cache shape specializations in the common C++ TVM FFI dispatcher and preserve CUDA fallbacks. Add independent numerical/capacity tests, reproducible benchmarks and profiling commands. Validate 55 direct cases, 52 PyTorch integration cases and 146 common C++ cases; boundary/extreme memcheck passes. On one GB200, improve all nine measured shapes over the grouped CUDA kernel. Large shapes reach 5.9-6.4 TB/s effective logical bandwidth; Nsight Compute measures 6.15 TB/s physical DRAM traffic. Column-only performance matches upstream cuDNN; the small extra cost with both TE scale outputs is explained by the added rowwise scale output. Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Measure the native CUDA and cached CuTeDSL paths through the same public grouped C API, using a C++ timing loop to exclude Python and ctypes overhead. Drain queues outside timing, report bounded async batches and graph capture separately, and calibrate thread CPU clocks. Also measure the PyTorch binding with prequantized grouped inputs, cached device offsets and output allocation included. Alternate backend order across nine batches of 1000 calls and verify identical outputs. On a GB200/Grace host, CuTeDSL adds about 0.6-0.8 us per preallocated batched C API dispatch and 3-4 us per full PyTorch binding call. Record all batch statistics, methodology, environment and reproduction commands. Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
for more information, see https://pre-commit.ci
Expose one grouped C API with an optional BF16 dequantized output. Select the faster columnwise requantization kernel when that output is absent, and retain the fused materialization kernel when it is requested. Consolidate the PyTorch binding and preserve grouped shape, scale-layout, capacity-tail and offsets-only coverage. Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Emit optional BF16 values directly from decoded registers without extra shared memory. Specialize cached TVM-FFI functions on the output option and retain native CUDA fallback for unsupported configurations. Use narrow tiles when the doubled tile count still fits in one SM wave. Add a preallocated C API benchmark that checks all outputs, identifies both kernels, and separates compilation from CUDA graph GPU timing. On one GB200, median BF16-output times across nine 100-call batches improve from 3.27 to 2.97 us at 1024x256, 8.38 to 6.07 us at 8192x1024, and 111.52 to 90.29 us at 16384x8192. Validate 146 common requantization tests, 171 focused PyTorch tests, and all 72 common materialization cases after tile tuning. Check both input FP8 formats, scale layouts, optional BF16 output, empty groups, capacity tails, and CUDA fallback. Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Select the scaled FP8-to-BF16 instruction only when the CuTeDSL compiler supports CUDA 13.2. Otherwise, use the native-equivalent FP16 conversion and BF16 scale multiplication sequence. Exercise automatic and portable decoding for both FP8 formats, including every FP8 encoding at extreme scales. Validation: 235 direct requantization tests passed with each CUDA 12.9 and CUDA 13.4 compiler on GB200. Pre-commit and focused pylint passed. Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
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Description
Add a fused grouped MXFP8 requantization path for Blackwell GPUs. The new operation converts compact rowwise MXFP8 input into columnwise E4M3 MXFP8 without materializing an intermediate high-precision tensor in global memory.
This reduces memory traffic compared with separate grouped dequantization and quantization calls. The kernel uses a tiled TMA pipeline and packed data movement/conversion operations, and supports both compact and GEMM-swizzled output scaling factors. The quantization configuration selects either an FP32 intermediate or a faster BF16 intermediate.
Type of change
Changes
Please list the changes introduced in this PR:
nvte_group_requantize_mxfp8C API for fused grouped rowwise-to-columnwise MXFP8 requantization.Checklist: