PRBS Testing on Celestica DX010

PRBS (Pseudo-Random Bit Sequence) is a method for measuring the raw bit error rate of a serial link at the physical layer. A known pattern is transmitted on a SerDes lane, and the receiver checks every bit against the expected sequence — any mismatch is a bit error. This reveals signal integrity problems (bad cables, marginal connectors, PCB defects, SerDes issues) without relying on FEC or upper-layer protocols.

In this project we perform PRBS testing on a Celestica DX010 switch running SONiC. The goals are:

• Validate physical-layer health of individual ports and lanes
• Measure pre-FEC BER using the Broadcom diagnostic shell
• Use loopback modules to isolate local hardware from cable/remote issues
• Document the procedures for repeatable lab testing

Document	Description
PRBS Fundamentals	Theory, polynomials, LFSR, BER thresholds, loopback modes
PRBS on Broadcom	Broadcom diagnostic shell commands, full reference

Test Setup

• Switch: Celestica DX010 (Tomahawk ASIC, 32x QSFP28 ports)
• Loopback module: 10Gtek 100G QSFP28 Loopback (0 dB, 3.5 W)

The loopback module connects TX lanes back to RX lanes at the cage, enabling external loopback PRBS without a cable or remote device. For background on loopback modes and test progression, see Loopback Modes.

Port mapping: SONiC interface → BCM SDK port name

Start from SONiC to identify the port and its lanes:

admin@sonic:~$ show interfaces status
  Interface            Lanes    Speed    MTU    FEC    Alias    Vlan    Oper    Admin             Type    Asym PFC
-----------  ---------------  -------  -----  -----  -------  ------  ------  -------  ---------------  ----------
...
Ethernet96      17,18,19,20     100G   9100     rs    Eth25   routed      up       up  QSFP28 or later         off
...

Each 100G port uses 4 SerDes lanes at 25G NRZ each. The lane numbers shown here (e.g., 17–20) are physical port numbers inside the ASIC.

In the diagnostic shell, use ps to find the corresponding SDK port names.

drivshell> ps
...
      ce24( 17)  up     4  100G  FD   SW  No   Forward   ← Eth25, loopback module inserted
      xe72( 18)  !ena   1   25G  FD None  No   Disable
      xe73( 19)  !ena   1   25G  FD None  No   Disable
      xe74( 20)  !ena   1   25G  FD None  No   Disable
...

The number in parentheses in ps is the logical port number. Use show portmap to see both logical and physical columns if needed. On Tomahawk, ce = 100G ports, xe = 25G individual lanes. The ce port occupies the first physical lane and spans all 4:

BCM SDK name	Lanes covered	Role
ce24	phys 17, 18, 19, 20	100G port — lane 0 + aggregate of all 4 lanes
xe72	phys 18	Lane 1 only (disabled in 100G mode)
xe73	phys 19	Lane 2 only (disabled in 100G mode)
xe74	phys 20	Lane 3 only (disabled in 100G mode)

Running phy diag ce24 prbs starts PRBS on all 4 lanes simultaneously and reports results per-lane. You cannot test a single lane in isolation without breaking out the port to 4x25G (which would replace the ce port with four independent xe ports).

Quick Start: PHY PRBS on DX010

Enter the diagnostic shell

docker exec -it syncd bash
bcmsh

External loopback test (with QSFP28 loopback module)

With the loopback module inserted (link shows "up" in ps), the module provides the physical loop — no LoopBack= setting needed.

Important: The port must be link-up before starting PRBS — confirm with ps ce24. Linkscan must be disabled before starting PRBS. When the PRBS generator replaces normal data on the TX lanes, the PCS reports link-down. If linkscan is active, it re-initializes the SerDes and prevents the PRBS checker from locking.

drivshell> ps ce24        # confirm link is up
drivshell> linkscan off
drivshell> phy diag ce24 prbs set p=3

# Wait 60+ seconds for errors to accumulate

drivshell> phy diag ce24 prbs get
drivshell> phy diag ce24 prbs clear
drivshell> linkscan on

Expected output for a healthy link:

ce24 (17):  PRBS OK!

A result of -2 errors means the checker did not lock — usually because the port was not link-up before starting PRBS. If errors are reported, calculate BER:

BER = error_count / (25G × 4 lanes × duration_seconds)
    = error_count / (100,000,000,000 × duration_seconds)

Per-lane signal diagnostics — dsc

The dsc (Digital Signal Conditioning) command shows per-lane signal quality — signal detect, CDR lock, eye margins, DFE taps, and TX equalization. It can be run with or without PRBS active.

drivshell> phy diag ce24 dsc

Example output (loopback module, all lanes healthy):

LN  SD LCK  EYE(L,R,U,D)
 0   1   1  312,343,132,129
 1   1   1  328,373,137,132
 2   1   1  312,359,137,132
 3   1   1  296,359,144,141

Field	Meaning
SD	Signal Detect (1 = signal present)
LCK	CDR Lock (1 = clock recovery locked)
EYE L/R	Horizontal eye margin (mUI)
EYE U/D	Vertical eye margin (mV-equivalent)
DFE	Decision Feedback Equalizer tap values
TXEQ	TX FIR pre/main/post cursor settings