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1. rtl-to-gdsii-picorv32 rtl-to-gdsii-picorv32 Public

   Complete RTL-to-GDSII implementation of the PicoRV32 RISC-V core using Cadence Xcelium, Genus, Innovus and Tempus (180nm) with 100MHz timing closure.

   Verilog 1 2

2. 6T-SRAM-Characterization 6T-SRAM-Characterization Public

   6T SRAM bitcell characterization in Cadence Virtuoso (DC + transient) with automated HSNM/RSNM extraction from butterfly CSVs (Python).

   Python

3. LZ77_AXI-Stream_Decompressor LZ77_AXI-Stream_Decompressor Public

   LZ77 decompressor in SystemVerilog with AXI-Stream wrapper, FIFO backpressure handling, and self-checking simulation.

   SystemVerilog 1

4. SystemVerilog_Practise SystemVerilog_Practise Public

   SystemVerilog RTL practice repo for improving RTL Design and Verification skills.

   SystemVerilog