This repository contains Verilog RTL implementations of basic combinational logic circuits commonly used in digital design. The goal is to provide clean, synthesizable, and easy-to-understand code suitable for beginners and VLSI learners.
The collection includes modules such as:
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Encoders / Decoders
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Multiplexers / Demultiplexers
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Adders (Half & Full Adders)
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Subtractors (Half & Full Subtractors)
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Multiplexer / Demultiplexer
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Arithmetic & Logic Unit (ALU)
Each design is written using Register Transfer Level (RTL) modeling with clear structure and comments. Testbenches are also included for functional verification using simulation tooL like Vivado.
This repository serves as a foundation for understanding how combinational circuits are modeled in Verilog and verified through simulations.