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Opcodes
This is Version 2 of the CPU design.
Bit Addressing mode (plus the NOOP instruction) has bits 7 - 4 set to 0000. Bit 3 specifies the operation (set or clear). Bits 2 - 0 specify the bit position or flag.
Indirect addressing mode has bits 7 - 4 set to 0010. Bits 3 - 0 specify the individual instruction.
Implicit addressing mode has bit 7 - 4 set to 0011. Bits 3 - 0 specify the individual instruction.
Direct addressing mode (plus the HALT instruction) has bits 7 - 6 set to 01. Bits 5 - 0 specify the individual instruction.
Immediate addressing mode has bit 7 set to 1. Bits 6 - 4 specify the register and nibble. Bits 3 - 0 contain the immediate value to be loaded.
Opcodes which are not listed are reserved for future use. Functionality of unlisted opcodes should not be assumed to work the same in future iterations of the CPU.
Bit Addressing Mode (and NOOP)
Bit fields
Opcode Mnemonic 000 r v bbb
------ -------- -----------
00 NOOP 000 0 0 000
04 BCFL 4 000 0 0 100 ; or BCFL V
05 BCFL 5 000 0 0 101 ; or BCFL C
06 BCFL 6 000 0 0 110 ; or BCFL Z
07 BCFL 7 000 0 0 111 ; or BCFL S
0C BSFL 4 000 0 1 100 ; or BSFL V
0D BSFL 5 000 0 1 101 ; or BSFL C
0E BSFL 6 000 0 1 110 ; or BSFL Z
0F BSFL 7 000 0 1 111 ; or BSFL S
Indirect Addressing Mode
Bit fields
Opcode Mnemonic 0010 iiii
------ --------- ----------
20 LOAD (MR) 0010 0000
21 STOR (MR) 0010 0001
24 JUMP 0010 0100
28 JPVC 0010 1000
29 JPVS 0010 1001
2A JPCC 0010 1010
2B JPCS 0010 1011
2C JPZC 0010 1100
2D JPZS 0010 1101
2E JPSC 0010 1110
2F JPSS 0010 1111
Implicit Mode
Bit fields
Opcode Mnemonic 0011 dddd
------ -------- ----------
30 PUSH AA 0011 0000
31 PUSH FL 0011 0001
34 POPP AA 0011 0100
35 POPP FL 0011 0101
Direct Mode (and HALT)
Bit fields
Opcode Mnemonic 01 000000
------ ----------- ----------
40 MOVE AB->AA 01 000000
41 MOVE AC->AA 01 000001
42 MOVE SL->AA 01 000010
43 MOVE SH->AA 01 000011
44 MOVE ML->AA 01 000100
45 MOVE MH->AA 01 000101
46 MOVE JL->AA 01 000110
47 MOVE JH->AA 01 000111
48 MOVE AA->AB 01 001000
49 MOVE AA->AC 01 001001
4A MOVE AA->SL 01 001010
4B MOVE AA->SH 01 001011
4C MOVE AA->ML 01 001100
4D MOVE AA->MH 01 001101
4E MOVE AA->JL 01 001110
4F MOVE AA->JH 01 001111
50 COMP 01 010000
51 SUBB 01 010001
52 ADDD 01 010010
53 ANDD 01 010011
54 ORRR 01 010100
55 XORR 01 010101
56 NAND 01 010110
57 NORR 01 010111
58 NOTT 01 011000
59 NEGA 01 011001
5A XNOR 01 011010
5B SHRL 01 011011
5C SHLL 01 011100
5D SHRA 01 011101
5E SRLC 01 011110
5F SLLC 01 011111
60 INCA 01 100000
61 DECA 01 100001
62 INCB 01 100010
63 INCC 01 100011
64 INCM 01 100100
68 LDA0 01 101000
69 LDB0 01 101001
6A LDC0 01 101010
7F HALT 01 111111
Immediate Mode
Bit fields
Opcode Mnemonic 1 ooo dddd
------ -------- ----------
8x LDAL #d 1 000 dddd
9x LDAH #d 1 001 dddd
Ax LDBL #d 1 010 dddd
Bx LDBH #d 1 011 dddd
Cx LJLL #d 1 100 dddd
Dx LJLH #d 1 101 dddd
Ex LJHL #d 1 110 dddd
Fx LJHH #d 1 111 dddd
| Date | Changes |
|---|---|
| 13-Oct-2025 | Created - Design Version 2 |
| 17-Oct-2025 | Opcode values re-arranged |
| 18-Oct-2025 | Optimizing the instruction set, better addressing mode grouping |
| 25-Oct-2025 | Scale back PUSH, POPP; add EXCH
|
| 06-Nov-2025 | Rearranged Bit Addressing opcodes so that NOOP can have opcode $00 |
| 06-Dec-2025 | Instruction/opcode changes, see 06-Dec-2025 blog entry |