xUSL/GFX: Add GFX initialization

xUSL/CCX/Common/Kconfig

@@ -5,7 +5,7 @@
 # ------------------------------ APIC Mode --------------------------
 choice
     prompt  "APIC - operational mode for this plaltform"
-    default CHOICE_APIC_AUTO
+    default APIC_AUTO
     help
         Ref: typedef enum{} APIC_MODE;
 

xUSL/GFX/Common/Gfx.h

@@ -8,6 +8,7 @@
 
 
 #include <xSIM.h>
+#include <APOB/Common/ApobCmn.h>
 #include <GFX/GfxClass-api.h>
 #include <GFX/Common/GfxDisplayPhySettings.h>
 #include <GFX/Common/GfxDisplayTypeSettings.h>
@@ -40,3 +41,9 @@ GetGfxDdiConfig (
   SIL_CONTEXT  *SilContext,
   uint32_t     *InfoDdiBlockDataSize
   );
+
+SIL_STATUS
+GetUmaInformation (
+  SIL_CONTEXT *SilContext,
+  MEMORY_HOLE_DESCRIPTOR *UmaRange
+  );

xUSL/GFX/Common/GfxConfigDflts.c

@@ -14,31 +14,31 @@ const GFXCLASS_INPUT_BLK GfxClassDflts = {
    * This becomes part of the IP API for the Host.
    */
   .AmdGfxOpenSilEnable = 1,
-  .CfgDisableAllNumAudioEndpoints = 0,
-  .DpHBR2Disable0 = 0,
-  .DpHBR3Disable0 = 0,
-  .DpHBR2Disable1 = 0,
-  .DpHBR3Disable1 = 0,
-  .DpHBR2Disable2 = 0,
-  .DpHBR3Disable2 = 0,
-  .DpHBR2Disable3 = 0,
-  .DpHBR3Disable3 = 0,
-  .HDMI2Disable0 = 0,
-  .HDMIRetimerCaps0 = 0,
-  .HDMI2Disable1 = 0,
-  .HDMIRetimerCaps1 = 0,
-  .HDMI2Disable2 = 0,
-  .HDMIRetimerCaps2 = 0,
-  .HDMI2Disable3 = 0,
-  .HDMIRetimerCaps3 = 0,
-  .PeiGopEnable = 0,
-  .SysInfoTconInstantOnLogoSupport = 0,
-  .CfgSysInfoGpuCapsDdsSupport = 0,
-  .CfgSysInfoGpuCapsBr3SdrSupport = 0,
-  .Usb4Rt0En = 0,
-  .Usb4Rt0DpTnlEn = 0,
-  .Usb4Rt1En = 0,
-  .Usb4Rt1DpTnlEn = 0,
+  .CfgDisableAllNumAudioEndpoints = false,
+  .DpHBR2Disable0 = false,
+  .DpHBR3Disable0 = false,
+  .DpHBR2Disable1 = false,
+  .DpHBR3Disable1 = false,
+  .DpHBR2Disable2 = false,
+  .DpHBR3Disable2 = false,
+  .DpHBR2Disable3 = false,
+  .DpHBR3Disable3 = false,
+  .HDMI2Disable0 = false,
+  .HDMIRetimerCaps0 = false,
+  .HDMI2Disable1 = false,
+  .HDMIRetimerCaps1 = false,
+  .HDMI2Disable2 = false,
+  .HDMIRetimerCaps2 = false,
+  .HDMI2Disable3 = false,
+  .HDMIRetimerCaps3 = false,
+  .PeiGopEnable = true,
+  .SysInfoTconInstantOnLogoSupport = false,
+  .CfgSysInfoGpuCapsDdsSupport = false,
+  .CfgSysInfoGpuCapsBr3SdrSupport = false,
+  .Usb4Rt0En = true,
+  .Usb4Rt0DpTnlEn = true,
+  .Usb4Rt1En = true,
+  .Usb4Rt1DpTnlEn = true,
   .AmdPreSilCtrl1 = 0,
   .AmdDisplayPhyTuningSettingTableHeader = 0,
   .AmdDisplayPhyTuningSettingTableContent = 0,
@@ -53,14 +53,16 @@ const GFXCLASS_INPUT_BLK GfxClassDflts = {
   .DisplayCapDdi3 = 0,
   .DisplayCapDdi4 = 0,
   .AmdBitMapDisaplyOnlyController = 0,
-  .CfgPcieRefClkSpreadSpectrum = 0,
+  .CfgPcieRefClkSpreadSpectrum = 375,
   .AmdDpPhyOverride = 0,
-  .BackLightPwmHz = 0,
-  .CfgMaxNumAudioEndpoints = 0,
-  .CfgIgpuControl = 0,
-  .DisplayFixVoltageSwing = 0,
+  .BackLightPwmHz = 200,
+  .CfgMaxNumAudioEndpoints = 4,
+  .CfgIgpuControl = 1,
+  .DisplayFixVoltageSwing = 2,
   .PwrOnVaryBlToBlon = 0,
   .PwrDownBloffToVaryBlOff = 0,
   .PwrOffDelay = 0,
   .Usb4DpiaDisable = 0,
+  .UmaMode = 2,
+  .AmdUmaCarveoutIndexMax = 1
 };

xUSL/GFX/Common/GfxDisplayPhySettings.h

@@ -8,64 +8,7 @@
 
 #pragma once
 
+#include "GfxV4.h"
+
 #define APU_TABLE_FORMAT_REVISION        1
 #define APU_TABLE_CONTENT_REVISION       0
-
-
-/****************************************************************************
- * Common header for all tables (Data table, Command function).
- * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
- * And the pointer actually points to this header.
- ****************************************************************************/
-//IPCLEAN_END
-typedef struct _atom_common_table_header {
-  uint16_t structuresize;
-  uint8_t  format_revision;   //mainly used for a hw function, when the parser is not backward compatible
-  uint8_t  content_revision;  //change it when a data table has a structure change,
-                              //or a hw function has a input/output parameter change
-} ATOM_COMMON_TABLE_HEADER;
-//IPCLEAN_START
-
-//ucEncoderMode
-typedef enum {
-  ATOM_ENCODER_MODE_DP = 0,
-  ATOM_ENCODER_MODE_DP_SST = 0,
-  ATOM_ENCODER_MODE_RESERVED = 1,
-  ATOM_ENCODER_MODE_DVI = 2,
-  ATOM_ENCODER_MODE_HDMI = 3,
-  ATOM_ENCODER_MODE_HDMI_FRL = 4,
-  ATOM_ENCODER_MODE_DP_AUDIO = 5,
-  ATOM_ENCODER_MODE_DP_MST = 5,
-  ATOM_ENCODER_MODE_DP2 = 8,
-  ATOM_ENCODER_MODE_CRT = 15,
-  ATOM_ENCODER_MODE_DVO = 16,
-} ATOM_ENCODE_MODE_DEF;
-
-typedef struct _atom_n6_display_phy_tuning_set {
-  uint8_t display_signal_type;
-  uint8_t phy_sel;
-  uint8_t preset_level;
-  uint8_t reserved1;
-  uint32_t reserved2;
-  uint32_t speed_upto;
-  uint8_t tx_vboost_level;
-  uint8_t tx_vreg_v2i;
-  uint8_t tx_vregdrv_byp;
-  uint8_t tx_term_cntl;
-  uint8_t tx_peak_level;
-  uint8_t tx_slew_en;
-  uint8_t tx_eq_pre;
-  uint8_t tx_eq_main;
-  uint8_t tx_eq_post;
-  uint8_t tx_en_inv_pre;
-  uint8_t tx_en_inv_post;
-  uint8_t tx_slew_ctrl_val;
-  uint32_t reserved4;
-  uint32_t reserved5;
-  uint32_t reserved6;
-} ATOM_N6_DISPLAY_PHY_TUNING_SET;
-
-typedef struct _atom_display_phy_tuning_info {
-  ATOM_COMMON_TABLE_HEADER table_header;
-  ATOM_N6_DISPLAY_PHY_TUNING_SET disp_phy_tuning[];
-} ATOM_DISPLAY_PHY_TUNING_INFO;

xUSL/GFX/Common/GfxInit.c

@@ -7,6 +7,8 @@
  */
 
 #include <string.h>
+#include <APOB/Common/ApobCmn.h>
+#include <APOB/ApobIp2Ip.h>
 #include <Nbio/NbioIp2Ip.h>
 #include <GFX/GfxClass-api.h>
 #include "Gfx.h"
@@ -181,40 +183,6 @@ GetGfxN6Config (
   return (void *)GfxN6InputData;
 }
 
-// Move to GfxInitPhx.c file
-void
-SilDumpDdiTable (
-  DDI_DESCRIPTOR         *DdiConfigData
-  )
-{
-  uint8_t index;
-
-  for (index = 0; index < 5; index++) {
-    GFX_TRACEPOINT(SIL_TRACE_INFO,
-      "SIL: Ddi ConnectorType 0x%x \n",
-      DdiConfigData[index].Ddi.ConnectorType
-      );
-    GFX_TRACEPOINT(SIL_TRACE_INFO,
-      "SIL: Ddi AuxInde 0x%x \n",
-      DdiConfigData[index].Ddi.AuxIndex
-      );
-    GFX_TRACEPOINT(SIL_TRACE_INFO,
-      "SIL: Ddi HdpIndex 0x%x \n",
-      DdiConfigData[index].Ddi.HdpIndex
-      );
-    GFX_TRACEPOINT(SIL_TRACE_INFO,
-      "SIL: Ddi LanePnInversionMask 0x%x \n",
-      DdiConfigData[index].Ddi.LanePnInversionMask
-      );
-    GFX_TRACEPOINT(SIL_TRACE_INFO,
-      "SIL: Ddi Flags 0x%x \n",
-      DdiConfigData[index].Ddi.Flags
-      );
-    GFX_TRACEPOINT(SIL_TRACE_INFO, "SIL: Flags 0x%x \n", DdiConfigData[index].Flags);
-  }
-
-}
-
 /**--------------------------------------------------------------------
  * GetGfxDdiConfig
  *
@@ -270,3 +238,49 @@ GetGfxDdiConfig (
   GFX_TRACEPOINT(SIL_TRACE_EXIT, "\n");
   return (void *)GfxDdiInputData;
 }
+
+
+SIL_STATUS
+GetUmaInformation (
+  SIL_CONTEXT *SilContext,
+  MEMORY_HOLE_DESCRIPTOR *UmaRange
+  )
+{
+  SIL_STATUS                          Status;
+  uint8_t                             MemRangeIndex;
+  APOB_SYSTEM_MEMORY_MAP_TYPE_STRUCT  *ApobEntry;
+  MEMORY_HOLE_DESCRIPTOR              *HoleMapPtr;
+  APOB_IP2IP_API                      *ApobIp2IpApi;
+
+  if (SilContext == NULL || UmaRange == NULL) {
+    return SilInvalidParameter;
+  }
+
+  Status = SilGetIp2IpApi(SilContext, SilId_ApobClass, (void **) &ApobIp2IpApi);
+  if ((Status != SilPass) || (ApobIp2IpApi == NULL)) {
+    assert(Status == SilPass);
+    return Status;
+  }
+
+  Status = ApobIp2IpApi->ApobAmdGetApobEntryInstance(SilContext,
+    APOB_FABRIC,
+    APOB_SYS_MAP_INFO_TYPE,
+    0,
+    0,
+    (APOB_TYPE_HEADER **) &ApobEntry
+    );
+  if (Status != SilPass) {
+    return Status;
+  }
+
+  /* Scan through all mem ranges to find the base address of UMA range. */
+  for (MemRangeIndex = 0; MemRangeIndex < ApobEntry->ApobSystemMap.NumberOfHoles; MemRangeIndex++) {
+    HoleMapPtr = &ApobEntry->ApobSystemMap.HoleInfo[MemRangeIndex];
+    if (HoleMapPtr->Type == UMA) {
+      memcpy(UmaRange, HoleMapPtr, sizeof(MEMORY_HOLE_DESCRIPTOR));
+      return SilPass;
+    }
+  }
+
+  return SilNotFound;
+}