Using BRAMs instead of LUTRAMs for big cfu storage

[bala122]

Hi @alanvgreen , @tcal-x ,
I just wanted to know if theres any way in which we can force the synthesis tool to use BRAMs for certain specific cfu storage variables instead of FFs or LUTRAMs. The issue is sometimes I hit an LUT resource usage limiit in 'place' under place & route, since I think all CFU storage is implemented as LUTRAMs.
Please let me know about this soon.. This could be helpful for some large designs of mine.
Thanks,
Bala.

[tcal-x]

Hi Bala, this is dependent on the synthesis tool. If you're writing the Verilog for the CFU directly, you probably need to add attributes to the declaration of the memory block. Please refer to the users manual for the synthesis tool you are using.

The VexRiscv has added some attributes; I'm not sure if they're supported by ALL tools or just some:

  (* no_rw_check , ram_style = "block" *) reg [22:0] ways_0_tags [0:63];

Another example at https://github.com/google/CFU-Playground/blob/main/soc/vexriscv/VexRiscv_FomuCfu.v#L1098

The no_rw_check attribute is specific for Yosys targetting Lattice FPGAs. Other tools will just ignore it.