I'm experimenting with Chisel and FuseSoC. Using the Chisel template Verilog can be generated with a command like
Note that it appears sbt wants all of its arguments as a single string.
Rather than jumping into a special sbt or Chisel generator I attempted to use the custom generator to run the above command. The list passed to the subprocess call should be ['sbt', 'runMain gcd.GCD']. However, the string split command used in the custom generator doesn't respect quotes and produces ['sbt', "'runMain", "gcd.GCD'"]. It appears that shlex.split handles quotes as I would expect
>>> cmd="sbt 'runMain gcd.GCD'"
>>> cmd.split()
['sbt', "'runMain", "gcd.GCD'"]
>>> import shlex
>>> shlex.split(cmd)
['sbt', 'runMain gcd.GCD']
II've not found a way of escaping quotes or the like that will work with the string split method, but am certainly open to suggestions. Would it make sense to change the split command used in the custom generator, or is this likely to cause too many compatibility issues?
I'm experimenting with Chisel and FuseSoC. Using the Chisel template Verilog can be generated with a command like
Note that it appears sbt wants all of its arguments as a single string.
Rather than jumping into a special sbt or Chisel generator I attempted to use the custom generator to run the above command. The list passed to the subprocess call should be
['sbt', 'runMain gcd.GCD']. However, the string split command used in the custom generator doesn't respect quotes and produces['sbt', "'runMain", "gcd.GCD'"]. It appears thatshlex.splithandles quotes as I would expectII've not found a way of escaping quotes or the like that will work with the string split method, but am certainly open to suggestions. Would it make sense to change the split command used in the custom generator, or is this likely to cause too many compatibility issues?