basic

Basic Programming Examples

These programming examples provide a good starting point to illustrate how to build commonly used compute kernels (both single-core and multi-core data processing pipelines). They serve to highlight how designs can be described in Python and lowered through the mlir-aie tool flow to an executable that runs on the NPU. Passthrough Kernel and Vector Scalar Mul are good designs to get started with. Please see section 3 of the programming guide for a more detailed guide on developing designs.

• Passthrough DMAs - Data movement memcpy using object FIFOs via DMAs only, without involving the AIE core.
• Passthrough Kernel - Vectorized memcpy via a single AIE core kernel.
• Passthrough PyKernel - Memcpy where the AIE kernel is written as an inline Python function rather than a C++ external function.
• Passthrough DMAs PLIO - Targets the Xilinx VCK5000, not Ryzen AI NPU. Demonstrates PLIO-connected soft DMAs in programmable logic.
• DMA Transpose - Matrix transpose using the Shim DMA with npu_dma_memcpy_nd.
• DMA Transpose Packet - Matrix transpose using packet-switched DMA flows.
• Chaining Channels - Demonstrates chaining multiple DMA buffer descriptors in sequence on a single channel.
• Combined Transpose - Matrix transpose combining Shim DMA strides with AIE core VSHUFFLE instructions.
• Shuffle Transpose - Matrix transpose using only AIE core VSHUFFLE instructions.
• Vector Scalar Add - Single tile increments every element of a vector by 1.
• Vector Scalar Mul - Single tile performs vector * scalar of size 4096 in 1024-element chunks.
• Vector Scalar Add Runlist - Vector scalar add using the run-list execution model.
• Vector Vector Add - Single tile performs vector + vector of size 1024.
• Vector Vector Add BDs Init Values - Vector addition with buffer descriptors pre-initialized with values.
• Vector Vector Modulo - Single tile performs vector % vector of size 1024.
• Vector Vector Multiply - Single tile performs vector * vector of size 1024.
• Vector Reduce Add - Single tile reduction returning the sum of a vector.
• Vector Reduce Max - Single tile reduction returning the max of a vector.
• Vector Reduce Min - Single tile reduction returning the min of a vector.
• Vector Exp - Element-wise $e^x$ using the AIE look-up table capability.
• Matrix Scalar Add - Single tile adds a scalar constant to every element of a 16x8 matrix.
• Matrix Multiplication - Single-core, multi-core (whole array), and matrix-vector multiply designs, plus sweep benchmarking infrastructure.
• Row Wise Bias Add - Adds a bias vector to each row of a matrix using DMA tiling.
• Event Trace - Demonstrates the AIE hardware trace unit for measuring kernel cycle counts and stall events. See also Section 4b of the programming guide.
• Packet Switch - Demonstrates packet-switched routing for multiplexing multiple data streams over shared interconnect.
• Tiling Exploration - Interactive exploration of TensorAccessPattern and TensorTiler2D for n-dimensional DMA tiling. Includes visualization tools.
• Memcpy - Exercise design. A parameterized multi-column memcpy with an intentionally unoptimized runtime sequence. The goal is to add task groups to achieve peak bandwidth. See getting_started/00_memcpy for the reference solution.