QEC architecture planner: select surface-code distance from a logical-error budget

[arniber21]

What to build

Add the first automatic fault-tolerant architecture-planning slice: select a surface-code distance for a workload from an explicit logical-failure budget and target assumptions, then compile the chosen workload through the existing QEC/NA path.

Today distance is supplied by the program or workload. The planner should evaluate a bounded candidate set, reject infeasible budgets honestly, and record why it selected a distance. The first version may use a clearly labeled analytic model; it must not turn that model into a threshold or hardware-calibration claim.

Design review is required for the logical-error model, candidate-distance policy, and interaction with user-specified distance.

Acceptance criteria

• An ADR defines the logical-failure budget, analytic model/evidence source, candidate distances, workload cycles, and precedence between automatic and explicit distance.
• A CLI/API request can ask for automatic surface-code distance selection under a target logical-failure budget.
• The planner evaluates each candidate with resource/error assumptions and selects the smallest feasible distance under the documented policy.
• Infeasible or under-specified requests fail with diagnostics listing the missing assumptions or evaluated candidates.
• The selected distance flows through QEC expansion, neutral-atom scheduling, verification, and resource reporting without a parallel manual path.
• Reports include requested budget, selected distance, candidate summary, evidence kind, assumptions, and safety margins.
• Tests cover at least two budgets selecting different distances, explicit-distance override behavior, and an infeasible budget.
• Documentation states that selection is an architecture estimate, not an experimentally validated threshold result.

Out of scope

• Automatic selection across arbitrary code families.
• Heterogeneous code conversion and magic-state factory co-optimization.
• Decoder implementation or real-hardware calibration.

Blocked by

None for the design and surface-code vertical slice.

Related

• Epic: QEC-aware neutral-atom compilation path #245 — QEC-aware compilation path
• Target model: neutral-atom physical error model for QEC reports #252 — neutral-atom physical error model
• QEC validation: fuse Stim/Sinter sampled results into compiler reports #280 — sampled validation in reports