arch/risc-v/k210: Add sysctl driver for clock and reset control.

Add sysctl driver for K210 SoC providing clock and reset control:
- Clock enable/disable with two-stage APB/peripheral enable pattern
- Peripheral reset control with proper timing
- Clock frequency query for PLL, CPU, APB buses, and peripherals
- PLL frequency calculation and CPU frequency configuration

The sysctl driver is built unconditionally for K210 boards as it
provides essential clock and reset control functionality.

Add Kconfig option:
- K210_CPU_FREQ: Target CPU frequency in Hz (default 400MHz)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>

Author: no1wudi

arch/risc-v/src/k210/CMakeLists.txt

@@ -26,6 +26,8 @@ list(APPEND SRCS k210_timerisr.c k210_allocateheap.c k210_clockconfig.c)
 
 list(APPEND SRCS k210_lowputc.c k210_serial.c k210_fpioa.c k210_gpiohs.c)
 
+list(APPEND SRCS k210_sysctl.c)
+
 if(CONFIG_BUILD_PROTECTED)
   list(APPEND SRCS k210_userspace.c)
 endif()

arch/risc-v/src/k210/Kconfig

@@ -27,6 +27,16 @@ config K210_UART0
 
 endmenu
 
+config K210_CPU_FREQ
+	int "K210 CPU target frequency (Hz)"
+	default 400000000
+	range 40000000 600000000
+	depends on ARCH_CHIP_K210
+	---help---
+		Set the K210 CPU target frequency in Hz.
+		Default is 400000000 (400 MHz).
+		Valid range: 40000000-600000000 Hz (40-600 MHz).
+
 menu "K210 Others"
 
 config K210_WITH_QEMU

arch/risc-v/src/k210/Make.defs

@@ -30,7 +30,7 @@ HEAD_ASRC = k210_head.S
 CHIP_CSRCS  = k210_allocateheap.c k210_clockconfig.c
 CHIP_CSRCS += k210_irq.c k210_irq_dispatch.c
 CHIP_CSRCS += k210_lowputc.c k210_serial.c k210_fpioa.c
-CHIP_CSRCS += k210_start.c k210_timerisr.c k210_gpiohs.c
+CHIP_CSRCS += k210_start.c k210_timerisr.c k210_gpiohs.c k210_sysctl.c
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CHIP_CSRCS += k210_userspace.c

arch/risc-v/src/k210/hardware/k210_sysctl.h

@@ -35,6 +35,7 @@
 
 #include "riscv_internal.h"
 #include "k210_clockconfig.h"
+#include "k210_sysctl.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -46,7 +47,7 @@
  * Private Data
  ****************************************************************************/
 
-static uint32_t g_cpu_clock = 416000000;
+static uint32_t g_cpu_clock = CONFIG_K210_CPU_FREQ;
 
 /****************************************************************************
  * Public Functions
@@ -90,22 +91,43 @@ void k210_clockconfig(void)
 {
 #ifndef CONFIG_K210_WITH_QEMU
   uint32_t clksel0;
+  uint32_t div;
 
-  /* Obtain clock selector for ACLK */
+  /* Initialize sysctl driver */
 
-  clksel0 = getreg32(K210_SYSCTL_CLKSEL0);
+  k210_sysctl_init();
 
-  if (1 == CLKSEL0_ACLK_SEL(clksel0))
-    {
-      /* PLL0 selected */
+  /* Wait for PLL0 to lock before configuring clocks */
 
-      g_cpu_clock = k210_get_pll0clk() / 2;
-    }
-  else
+  while (!k210_sysctl_pll_is_locked(K210_SYSCTL_PLL0))
     {
-      /* OSC selected */
+      up_mdelay(1);
+    }
+
+  /* Enable essential system clocks */
 
-      g_cpu_clock = OSC_FREQ;
+  k210_sysctl_clock_enable(K210_CLOCK_CPU);
+  k210_sysctl_clock_enable(K210_CLOCK_SRAM0);
+  k210_sysctl_clock_enable(K210_CLOCK_SRAM1);
+
+  /* Use new frequency API to update g_cpu_clock */
+
+  g_cpu_clock = k210_sysctl_clock_get_freq(K210_CLOCK_CPU);
+  if (g_cpu_clock == 0)
+    {
+      /* Fallback to PLL frequency calculation if new API fails */
+
+      clksel0 = getreg32(K210_SYSCTL_CLKSEL0);
+
+      if (1 == CLKSEL0_ACLK_SEL(clksel0))
+        {
+          div = (clksel0 & CLKSEL0_ACLK_DIV_MASK) >> CLKSEL0_ACLK_DIV_SHIFT;
+          g_cpu_clock = k210_get_pll0clk() / (2u << div);
+        }
+      else
+        {
+          g_cpu_clock = OSC_FREQ;
+        }
     }
 
   /* Workaround for stabilization */