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Feature tutorials illustrate specific features of Vitis development flow, some features may not be required by all designs but are still useful for some use cases.
| Tutorial | Description |
| Vitis Functional Simulation | This tutorial introduces Vitis Functional Simulation (VFS), a new feature that allows you to functionally simulate AI Engine graphs and/or HLS kernels in both MATLAB® and Python™ environments on Linux. Simple examples are provided to show users how to get started. For more information on Vitis Functional Simulation, refer to Chapter 6 of Embedded Design Development Using Vitis User Guide (UG1701) . |
| Vitis Subsystem Simulation | This tutorial demontrates a new feature, Vitis Subsystem Simulation, which enables you to simulate AI Engine + PL designs in a RTL testbench environment. By running the AI Engine simulation encapsulated in a VSS component, the interaction between AI Engine PLIO and custom RTL can be analyzed and verified without having to go through the full system emulation flow. |
| Vitis Hardware in the Loop | This tutorial demonstrates Vitis Hardware in the Loop (HIL), which enables real-time verification of DSP-based systems by executing the actual design on a development board equipped with a Versal™ adaptive SoC. It demonstrates a complete Vitis HIL workflow using a polyphase channelizer as the design under test. |
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