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Test drive select_ci_image risc-v CI #531: Pull request #203 synchronize by TheDeepestSpace
7m 4s TheDeepestSpace:boris/ci-for-external-contributors
TheDeepestSpace:boris/ci-for-external-contributors
7m 4s
Test drive select_ci_image risc-v CI #530: Pull request #203 opened by TheDeepestSpace
1h 48m 34s TheDeepestSpace:boris/ci-for-external-contributors
TheDeepestSpace:boris/ci-for-external-contributors
1h 48m 34s
Add select_ci_image risc-v CI #529: Pull request #201 synchronize by TheDeepestSpace
8m 4s boris/ci-for-external-contributors
boris/ci-for-external-contributors
8m 4s
Test drive select_ci_image risc-v CI #528: Pull request #202 opened by TheDeepestSpace
7s TheDeepestSpace:boris/ci-for-external-contributors
TheDeepestSpace:boris/ci-for-external-contributors
7s
Add select_ci_image risc-v CI #527: Pull request #201 opened by TheDeepestSpace
7m 56s boris/ci-for-external-contributors
boris/ci-for-external-contributors
7m 56s
Refactor ALU to use SystemVerilog enums and fix branch logic risc-v CI #525: Pull request #200 opened by RexPaster
1m 43s RexPaster:alu-enumeration
RexPaster:alu-enumeration
1m 43s
UART peripheral risc-v CI #523: Pull request #154 synchronize by TheDeepestSpace
8m 56s uart_peripheral
uart_peripheral
8m 56s
UART peripheral risc-v CI #522: Pull request #154 synchronize by TheDeepestSpace
9m 10s uart_peripheral
uart_peripheral
9m 10s
UART peripheral risc-v CI #521: Pull request #154 synchronize by TheDeepestSpace
8m 50s uart_peripheral
uart_peripheral
8m 50s
UART peripheral risc-v CI #520: Pull request #154 synchronize by TheDeepestSpace
9m 0s uart_peripheral
uart_peripheral
9m 0s
Pipeline V1 risc-v CI #519: Pull request #159 synchronize by TheDeepestSpace
14m 12s pipeline-v1
pipeline-v1
14m 12s
Pr187 - Verilator warnings risc-v CI #518: Pull request #188 synchronize by MM871
4m 0s pr187
pr187
4m 0s
Changes to the fetch stage risc-v CI #517: Pull request #197 synchronize by thatlittlegit
3m 1s duncanm/fetch-stage-again
duncanm/fetch-stage-again
3m 1s
Changes to the fetch stage risc-v CI #516: Pull request #197 opened by thatlittlegit
16m 19s duncanm/fetch-stage-again
duncanm/fetch-stage-again
16m 19s
implemented zbb instructions (logic-not, min/max, sign/zero ext) risc-v CI #515: Pull request #196 synchronize by MSh-786
9m 0s zbb-implementation
zbb-implementation
9m 0s
implemented zbb instructions (logic-not, min/max, sign/zero ext) risc-v CI #514: Pull request #196 opened by MSh-786
3m 15s zbb-implementation
zbb-implementation
3m 15s
Add Zbs single-bit operations implementation (RV32, SystemVerilog) risc-v CI #513: Pull request #191 synchronize by jeff-7
8m 58s zbs-implementation
zbs-implementation
8m 58s
Merge pull request #193 from UTOSS/zba-format-update risc-v CI #512: Commit daec300 pushed by Parzival129
12m 12s main
main
12m 12s
Zba format update risc-v CI #511: Pull request #193 opened by Parzival129
18m 29s zba-format-update
zba-format-update
18m 29s
Update zba to use proper ISA specification risc-v CI #510: Pull request #189 synchronize by Parzival129
14m 44s zba-implementation
zba-implementation
14m 44s
Add Zbs single-bit operations implementation (RV32, SystemVerilog) risc-v CI #509: Pull request #191 synchronize by jeff-7
7m 43s zbs-implementation
zbs-implementation
7m 43s
Add Zbs single-bit operations implementation (RV32, SystemVerilog) risc-v CI #508: Pull request #191 synchronize by jeff-7
8m 6s zbs-implementation
zbs-implementation
8m 6s
Add Zbs single-bit operations implementation (RV32, SystemVerilog) risc-v CI #507: Pull request #191 synchronize by jeff-7
8m 3s zbs-implementation
zbs-implementation
8m 3s
Add Zbs single-bit operations implementation (RV32, SystemVerilog) risc-v CI #506: Pull request #191 synchronize by jeff-7
4m 7s zbs-implementation
zbs-implementation
4m 7s
Add Zbs single-bit operations implementation (RV32, SystemVerilog) risc-v CI #505: Pull request #191 synchronize by jeff-7
8m 3s zbs-implementation
zbs-implementation
8m 3s