From 522d7eb1931f3faac8a6b7f5fbdbd770b4516e42 Mon Sep 17 00:00:00 2001 From: Lukasz Kutyla Date: Wed, 18 Feb 2026 06:43:37 +0100 Subject: [PATCH] soc/intel/pmclib: Fix boot issue after power loss when using USB-C PD FIZZ boards are unable to boot after power loss if USB-C PD is used to initially power them on when CFR `Restore AC power after loss` (`power_on_after_fail`) is set to: - `Power off (S5)` - Always. - `Previous state` - Only after a clean shutdown. Both options result in Intel chipset after G3 being set by coreboot to keep the device off when power is restored (`Previous state` only after a clean shutdown). The issue is likely related to some sort of miscommunication between chipset and ChromeEC, perhaps due to USB-C PD induced delays (barrel jack not affected), where ChromeEC fails to bring the system up and gives up. Since this affects EC RO there is no safe way of mitigating this issue from EC side. The solution is to always make sure that chipset after G3 is set to `auto on`, and let EC handle the rest if EC manages after G3. Signed-off-by: Lukasz Kutyla --- src/ec/google/chromeec/Kconfig | 1 + src/mainboard/Kconfig | 3 +++ src/soc/intel/common/block/pmc/pmclib.c | 10 ++++++++-- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 0ec58e9cdbe..88f42c7f409 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -203,6 +203,7 @@ config EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG config EC_GOOGLE_CHROMEEC_AFTER_G3_STATE bool "Enable syncing ChromeEC After G3 State with CFR at boot" depends on DRIVERS_OPTION_CFR_ENABLED + select HAVE_EC_POWER_STATE_AFTER_FAILURE help Enable syncing ChromeEC After G3 State with CFR at boot via host command, otherwise ChromeEC default compiled after G3 behavior diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 40080125a38..80645904c56 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -202,6 +202,9 @@ config ENABLE_POWER_BUTTON def_bool y if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_ENABLE def_bool n if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_DISABLE +config HAVE_EC_POWER_STATE_AFTER_FAILURE + bool + config HAVE_POWER_STATE_AFTER_FAILURE bool diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 64b9bb997c6..f5e7ba5e3e8 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -776,8 +776,14 @@ void pmc_clear_pmcon_sts(void) void pmc_set_power_failure_state(const bool target_on) { - const unsigned int state = get_uint_option("power_on_after_fail", - CONFIG_MAINBOARD_POWER_FAILURE_STATE); + /* + * Always set to "auto on" to avoid potential conflicts with EC that + * can result in the inability to boot if EC handles after G3. + */ + const unsigned int state = (CONFIG(HAVE_EC_POWER_STATE_AFTER_FAILURE) ? + MAINBOARD_POWER_STATE_ON : + get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE)); /* * On the shutdown path (target_on == false), we only need to