diff --git a/library/SubcircuitLibrary/54f64/3_and-cache.lib b/library/SubcircuitLibrary/54f64/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/54f64/3_and.cir b/library/SubcircuitLibrary/54f64/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/54f64/3_and.cir.out b/library/SubcircuitLibrary/54f64/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/54f64/3_and.pro b/library/SubcircuitLibrary/54f64/3_and.pro new file mode 100644 index 000000000..06813ca78 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/54f64/3_and.sch b/library/SubcircuitLibrary/54f64/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/54f64/3_and.sub b/library/SubcircuitLibrary/54f64/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/54f64/3_and_Previous_Values.xml b/library/SubcircuitLibrary/54f64/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/54f64/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/54f64/4_and-cache.lib b/library/SubcircuitLibrary/54f64/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/54f64/4_and-rescue.lib b/library/SubcircuitLibrary/54f64/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/54f64/4_and.cir b/library/SubcircuitLibrary/54f64/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/54f64/4_and.cir.out b/library/SubcircuitLibrary/54f64/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/54f64/4_and.pro b/library/SubcircuitLibrary/54f64/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/54f64/4_and.sch b/library/SubcircuitLibrary/54f64/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/library/SubcircuitLibrary/54f64/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/54f64/4_and.sub b/library/SubcircuitLibrary/54f64/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/54f64/4_and_Previous_Values.xml b/library/SubcircuitLibrary/54f64/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/library/SubcircuitLibrary/54f64/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/54f64/54f64-cache.lib b/library/SubcircuitLibrary/54f64/54f64-cache.lib new file mode 100644 index 000000000..8c472fe4b --- /dev/null +++ b/library/SubcircuitLibrary/54f64/54f64-cache.lib @@ -0,0 +1,117 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/54f64/54f64.cir b/library/SubcircuitLibrary/54f64/54f64.cir new file mode 100644 index 000000000..5096a65ab --- /dev/null +++ b/library/SubcircuitLibrary/54f64/54f64.cir @@ -0,0 +1,18 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\54f64\54f64.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/22/25 13:59:39 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U6 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U2-Pad1_ d_and +X1 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U2-Pad2_ 3_and +U5 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad1_ d_and +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U3-Pad1_ d_nor +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_nor +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad8_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ PORT +X2 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad1_ Net-_U4-Pad2_ 4_and + +.end diff --git a/library/SubcircuitLibrary/54f64/54f64.cir.out b/library/SubcircuitLibrary/54f64/54f64.cir.out new file mode 100644 index 000000000..61545f26c --- /dev/null +++ b/library/SubcircuitLibrary/54f64/54f64.cir.out @@ -0,0 +1,36 @@ +* c:\fossee\esim\library\subcircuitlibrary\54f64\54f64.cir + +.include 4_and.sub +.include 3_and.sub +* u6 net-_u1-pad3_ net-_u1-pad2_ net-_u2-pad1_ d_and +x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u2-pad2_ 3_and +* u5 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad1_ d_and +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_nor +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_nor +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad8_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port +x2 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad1_ net-_u4-pad2_ 4_and +a1 [net-_u1-pad3_ net-_u1-pad2_ ] net-_u2-pad1_ u6 +a2 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad1_ u5 +a3 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4 +a4 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a5 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad8_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 250e-03 10e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/54f64/54f64.pro b/library/SubcircuitLibrary/54f64/54f64.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/54f64/54f64.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/54f64/54f64.sch b/library/SubcircuitLibrary/54f64/54f64.sch new file mode 100644 index 000000000..6145d3bd3 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/54f64.sch @@ -0,0 +1,366 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:54f64-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U6 +U 1 1 6857B47E +P 3750 2450 +F 0 "U6" H 3750 2450 60 0000 C CNN +F 1 "d_and" H 3800 2550 60 0000 C CNN +F 2 "" H 3750 2450 60 0000 C CNN +F 3 "" H 3750 2450 60 0000 C CNN + 1 3750 2450 + 0 1 1 0 +$EndComp +$Comp +L 3_and X1 +U 1 1 6857B510 +P 3100 3550 +F 0 "X1" H 3200 3500 60 0000 C CNN +F 1 "3_and" H 3250 3700 60 0000 C CNN +F 2 "" H 3100 3550 60 0000 C CNN +F 3 "" H 3100 3550 60 0000 C CNN + 1 3100 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 6857B571 +P 5300 3400 +F 0 "U5" H 5300 3400 60 0000 C CNN +F 1 "d_and" H 5350 3500 60 0000 C CNN +F 2 "" H 5300 3400 60 0000 C CNN +F 3 "" H 5300 3400 60 0000 C CNN + 1 5300 3400 + -1 0 0 1 +$EndComp +$Comp +L d_nor U4 +U 1 1 6857B59C +P 4550 4300 +F 0 "U4" H 4550 4300 60 0000 C CNN +F 1 "d_nor" H 4600 4400 60 0000 C CNN +F 2 "" H 4550 4300 60 0000 C CNN +F 3 "" H 4550 4300 60 0000 C CNN + 1 4550 4300 + 0 1 1 0 +$EndComp +$Comp +L d_nor U2 +U 1 1 6857B5EF +P 3900 4300 +F 0 "U2" H 3900 4300 60 0000 C CNN +F 1 "d_nor" H 3950 4400 60 0000 C CNN +F 2 "" H 3900 4300 60 0000 C CNN +F 3 "" H 3900 4300 60 0000 C CNN + 1 3900 4300 + 0 1 1 0 +$EndComp +$Comp +L d_nor U3 +U 1 1 6857B626 +P 4150 5450 +F 0 "U3" H 4150 5450 60 0000 C CNN +F 1 "d_nor" H 4200 5550 60 0000 C CNN +F 2 "" H 4150 5450 60 0000 C CNN +F 3 "" H 4150 5450 60 0000 C CNN + 1 4150 5450 + 0 1 1 0 +$EndComp +Wire Wire Line + 4850 3450 4650 3450 +Wire Wire Line + 4650 3450 4650 3850 +Wire Wire Line + 4550 2850 4550 3850 +Wire Wire Line + 3800 2900 4000 2900 +Wire Wire Line + 4000 2900 4000 3850 +Wire Wire Line + 3600 3500 3900 3500 +Wire Wire Line + 3900 3500 3900 3850 +Wire Wire Line + 3950 4750 3950 4950 +Wire Wire Line + 3950 4950 4150 4950 +Wire Wire Line + 4150 4950 4150 5000 +Wire Wire Line + 4600 4750 4600 4950 +Wire Wire Line + 4600 4950 4250 4950 +Wire Wire Line + 4250 4950 4250 5000 +$Comp +L PORT U1 +U 1 1 6857B6DC +P 4350 1150 +F 0 "U1" H 4400 1250 30 0000 C CNN +F 1 "PORT" H 4350 1150 30 0000 C CNN +F 2 "" H 4350 1150 60 0000 C CNN +F 3 "" H 4350 1150 60 0000 C CNN + 1 4350 1150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 6857B85D +P 3550 1350 +F 0 "U1" H 3600 1450 30 0000 C CNN +F 1 "PORT" H 3550 1350 30 0000 C CNN +F 2 "" H 3550 1350 60 0000 C CNN +F 3 "" H 3550 1350 60 0000 C CNN + 2 3550 1350 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 6857B8B4 +P 4000 1350 +F 0 "U1" H 4050 1450 30 0000 C CNN +F 1 "PORT" H 4000 1350 30 0000 C CNN +F 2 "" H 4000 1350 60 0000 C CNN +F 3 "" H 4000 1350 60 0000 C CNN + 3 4000 1350 + 0 1 1 0 +$EndComp +Wire Wire Line + 3550 1600 3750 1600 +Wire Wire Line + 3750 1600 3750 2000 +Wire Wire Line + 4000 1600 3850 1600 +Wire Wire Line + 3850 1600 3850 2000 +$Comp +L PORT U1 +U 4 1 6857B9B4 +P 2400 3150 +F 0 "U1" H 2450 3250 30 0000 C CNN +F 1 "PORT" H 2400 3150 30 0000 C CNN +F 2 "" H 2400 3150 60 0000 C CNN +F 3 "" H 2400 3150 60 0000 C CNN + 4 2400 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6857B9F5 +P 2400 3500 +F 0 "U1" H 2450 3600 30 0000 C CNN +F 1 "PORT" H 2400 3500 30 0000 C CNN +F 2 "" H 2400 3500 60 0000 C CNN +F 3 "" H 2400 3500 60 0000 C CNN + 5 2400 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6857BA3C +P 2400 3850 +F 0 "U1" H 2450 3950 30 0000 C CNN +F 1 "PORT" H 2400 3850 30 0000 C CNN +F 2 "" H 2400 3850 60 0000 C CNN +F 3 "" H 2400 3850 60 0000 C CNN + 6 2400 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2650 3150 2650 3400 +Wire Wire Line + 2650 3400 2750 3400 +Wire Wire Line + 2650 3500 2750 3500 +Wire Wire Line + 2650 3850 2650 3600 +Wire Wire Line + 2650 3600 2750 3600 +$Comp +L PORT U1 +U 8 1 6857BB79 +P 3950 6000 +F 0 "U1" H 4000 6100 30 0000 C CNN +F 1 "PORT" H 3950 6000 30 0000 C CNN +F 2 "" H 3950 6000 60 0000 C CNN +F 3 "" H 3950 6000 60 0000 C CNN + 8 3950 6000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6857BC54 +P 6300 3550 +F 0 "U1" H 6350 3650 30 0000 C CNN +F 1 "PORT" H 6300 3550 30 0000 C CNN +F 2 "" H 6300 3550 60 0000 C CNN +F 3 "" H 6300 3550 60 0000 C CNN + 9 6300 3550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6857BCA5 +P 6300 3300 +F 0 "U1" H 6350 3400 30 0000 C CNN +F 1 "PORT" H 6300 3300 30 0000 C CNN +F 2 "" H 6300 3300 60 0000 C CNN +F 3 "" H 6300 3300 60 0000 C CNN + 10 6300 3300 + -1 0 0 1 +$EndComp +Wire Wire Line + 5750 3500 5750 3550 +Wire Wire Line + 5750 3550 6050 3550 +Wire Wire Line + 5750 3400 5750 3300 +Wire Wire Line + 5750 3300 6050 3300 +$Comp +L 4_and X2 +U 1 1 6857BD7B +P 4550 2350 +F 0 "X2" H 4600 2300 60 0000 C CNN +F 1 "4_and" H 4650 2450 60 0000 C CNN +F 2 "" H 4550 2350 60 0000 C CNN +F 3 "" H 4550 2350 60 0000 C CNN + 1 4550 2350 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 6857BE36 +P 4550 1100 +F 0 "U1" H 4600 1200 30 0000 C CNN +F 1 "PORT" H 4550 1100 30 0000 C CNN +F 2 "" H 4550 1100 60 0000 C CNN +F 3 "" H 4550 1100 60 0000 C CNN + 11 4550 1100 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 6857BEAF +P 4750 1150 +F 0 "U1" H 4800 1250 30 0000 C CNN +F 1 "PORT" H 4750 1150 30 0000 C CNN +F 2 "" H 4750 1150 60 0000 C CNN +F 3 "" H 4750 1150 60 0000 C CNN + 12 4750 1150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 6857BEF8 +P 4950 1150 +F 0 "U1" H 5000 1250 30 0000 C CNN +F 1 "PORT" H 4950 1150 30 0000 C CNN +F 2 "" H 4950 1150 60 0000 C CNN +F 3 "" H 4950 1150 60 0000 C CNN + 13 4950 1150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4350 1400 4350 1800 +Wire Wire Line + 4350 1800 4400 1800 +Wire Wire Line + 4400 1800 4400 1950 +Wire Wire Line + 4550 1350 4550 1600 +Wire Wire Line + 4550 1600 4500 1600 +Wire Wire Line + 4500 1600 4500 1950 +Wire Wire Line + 4750 1400 4750 1600 +Wire Wire Line + 4750 1600 4600 1600 +Wire Wire Line + 4600 1600 4600 1950 +Wire Wire Line + 4950 1400 4950 1800 +Wire Wire Line + 4950 1800 4700 1800 +Wire Wire Line + 4700 1800 4700 1950 +Wire Wire Line + 4200 6000 4200 5900 +Text Notes 3650 1900 0 60 ~ 0 +a2 +Text Notes 3850 1950 0 60 ~ 0 +b2 +Text Notes 4200 1500 0 60 ~ 0 +a0\n +Text Notes 4400 1450 0 60 ~ 0 +b0\n +Text Notes 4600 1450 0 60 ~ 0 +c0\n +Text Notes 4800 1500 0 60 ~ 0 +d0\n +Text Notes 2750 3200 0 60 ~ 0 +a1 +Text Notes 2700 3500 0 60 ~ 0 +b1 +Text Notes 2700 3700 0 60 ~ 0 +c1 +Text Notes 5900 3200 0 60 ~ 0 +a3 +Text Notes 5950 3700 0 60 ~ 0 +b3 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/54f64/54f64.sub b/library/SubcircuitLibrary/54f64/54f64.sub new file mode 100644 index 000000000..aa1cb0783 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/54f64.sub @@ -0,0 +1,30 @@ +* Subcircuit 54f64 +.subckt 54f64 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ +* c:\fossee\esim\library\subcircuitlibrary\54f64\54f64.cir +.include 4_and.sub +.include 3_and.sub +* u6 net-_u1-pad3_ net-_u1-pad2_ net-_u2-pad1_ d_and +x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u2-pad2_ 3_and +* u5 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad1_ d_and +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_nor +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_nor +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad8_ d_nor +x2 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad1_ net-_u4-pad2_ 4_and +a1 [net-_u1-pad3_ net-_u1-pad2_ ] net-_u2-pad1_ u6 +a2 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad1_ u5 +a3 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4 +a4 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a5 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad8_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 54f64 \ No newline at end of file diff --git a/library/SubcircuitLibrary/54f64/54f64_Previous_Values.xml b/library/SubcircuitLibrary/54f64/54f64_Previous_Values.xml new file mode 100644 index 000000000..ecfdd7fd8 --- /dev/null +++ b/library/SubcircuitLibrary/54f64/54f64_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecd_andd_andd_nord_nord_norC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/54f64/analysis b/library/SubcircuitLibrary/54f64/analysis new file mode 100644 index 000000000..0a6c83b5a --- /dev/null +++ b/library/SubcircuitLibrary/54f64/analysis @@ -0,0 +1 @@ +.tran 250e-03 10e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74S182/3_and-cache.lib b/library/SubcircuitLibrary/74S182/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74S182/3_and.cir b/library/SubcircuitLibrary/74S182/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74S182/3_and.cir.out b/library/SubcircuitLibrary/74S182/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74S182/3_and.pro b/library/SubcircuitLibrary/74S182/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/74S182/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/74S182/3_and.sch b/library/SubcircuitLibrary/74S182/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74S182/3_and.sub b/library/SubcircuitLibrary/74S182/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/74S182/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74S182/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/74S182/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74S182/4_OR-cache.lib b/library/SubcircuitLibrary/74S182/4_OR-cache.lib new file mode 100644 index 000000000..155f5e601 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74S182/4_OR.cir b/library/SubcircuitLibrary/74S182/4_OR.cir new file mode 100644 index 000000000..b338b7b5f --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/74S182/4_OR.cir.out b/library/SubcircuitLibrary/74S182/4_OR.cir.out new file mode 100644 index 000000000..adb6b01be --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74S182/4_OR.pro b/library/SubcircuitLibrary/74S182/4_OR.pro new file mode 100644 index 000000000..881563ebd --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/74S182/4_OR.sch b/library/SubcircuitLibrary/74S182/4_OR.sch new file mode 100644 index 000000000..118968656 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74S182/4_OR.sub b/library/SubcircuitLibrary/74S182/4_OR.sub new file mode 100644 index 000000000..d1fd3a241 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/74S182/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/74S182/4_OR_Previous_Values.xml new file mode 100644 index 000000000..0683d9eb6 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74S182/4_and-cache.lib b/library/SubcircuitLibrary/74S182/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74S182/4_and-rescue.lib b/library/SubcircuitLibrary/74S182/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74S182/4_and.cir b/library/SubcircuitLibrary/74S182/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/74S182/4_and.cir.out b/library/SubcircuitLibrary/74S182/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74S182/4_and.pro b/library/SubcircuitLibrary/74S182/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/74S182/4_and.sch b/library/SubcircuitLibrary/74S182/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74S182/4_and.sub b/library/SubcircuitLibrary/74S182/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/74S182/4_and_Previous_Values.xml b/library/SubcircuitLibrary/74S182/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/library/SubcircuitLibrary/74S182/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74S182/74S182-cache.lib b/library/SubcircuitLibrary/74S182/74S182-cache.lib new file mode 100644 index 000000000..644604439 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/74S182-cache.lib @@ -0,0 +1,171 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74S182/74S182.cir b/library/SubcircuitLibrary/74S182/74S182.cir new file mode 100644 index 000000000..10f35aab7 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/74S182.cir @@ -0,0 +1,33 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74S182\74S182.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/22/25 09:40:55 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 P3_bar P2_bar P1_bar P0_bar Net-_U1-Pad7_ 4_OR +X4 G3_bar G2_bar G1_bar G0_bar Net-_X10-Pad1_ 4_and +X5 P1_bar G3_bar G2_bar G1_bar Net-_X10-Pad2_ 4_and +X6 P2_bar G3_bar G2_bar Net-_X10-Pad3_ 3_and +U2 P3_bar G3_bar Net-_U2-Pad3_ d_and +X7 G2_bar G1_bar G0_bar Net-_U20-Pad2_ Net-_X11-Pad1_ 4_and +X8 P0_bar G2_bar G1_bar G0_bar Net-_X11-Pad2_ 4_and +X9 P1_bar G2_bar G1_bar Net-_X11-Pad3_ 3_and +U3 P2_bar G2_bar Net-_U3-Pad3_ d_and +X2 G1_bar G0_bar Net-_U20-Pad2_ Net-_U8-Pad1_ 3_and +X3 P0_bar G1_bar G0_bar Net-_U8-Pad2_ 3_and +U4 P1_bar G1_bar Net-_U10-Pad2_ d_and +U5 G0_bar Net-_U20-Pad2_ Net-_U5-Pad3_ d_and +U6 P0_bar G0_bar Net-_U6-Pad3_ d_and +X10 Net-_X10-Pad1_ Net-_X10-Pad2_ Net-_X10-Pad3_ Net-_U2-Pad3_ Net-_U1-Pad10_ 4_OR +U7 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U1-Pad12_ d_nor +X11 Net-_X11-Pad1_ Net-_X11-Pad2_ Net-_X11-Pad3_ Net-_U3-Pad3_ Net-_U9-Pad1_ 4_OR +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U10-Pad1_ d_or +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U9 Net-_U9-Pad1_ Net-_U1-Pad9_ d_inverter +U11 Net-_U10-Pad3_ Net-_U1-Pad11_ d_inverter +U20 Cn Net-_U20-Pad2_ d_inverter +U1 G1_bar P1_bar G0_bar P0_bar G3_bar P3_bar Net-_U1-Pad7_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Cn G2_bar P2_bar PORT + +.end diff --git a/library/SubcircuitLibrary/74S182/74S182.cir.out b/library/SubcircuitLibrary/74S182/74S182.cir.out new file mode 100644 index 000000000..160f3f6fa --- /dev/null +++ b/library/SubcircuitLibrary/74S182/74S182.cir.out @@ -0,0 +1,70 @@ +* c:\fossee\esim\library\subcircuitlibrary\74s182\74s182.cir + +.include 4_OR.sub +.include 4_and.sub +.include 3_and.sub +x1 p3_bar p2_bar p1_bar p0_bar net-_u1-pad7_ 4_OR +x4 g3_bar g2_bar g1_bar g0_bar net-_x10-pad1_ 4_and +x5 p1_bar g3_bar g2_bar g1_bar net-_x10-pad2_ 4_and +x6 p2_bar g3_bar g2_bar net-_x10-pad3_ 3_and +* u2 p3_bar g3_bar net-_u2-pad3_ d_and +x7 g2_bar g1_bar g0_bar net-_u20-pad2_ net-_x11-pad1_ 4_and +x8 p0_bar g2_bar g1_bar g0_bar net-_x11-pad2_ 4_and +x9 p1_bar g2_bar g1_bar net-_x11-pad3_ 3_and +* u3 p2_bar g2_bar net-_u3-pad3_ d_and +x2 g1_bar g0_bar net-_u20-pad2_ net-_u8-pad1_ 3_and +x3 p0_bar g1_bar g0_bar net-_u8-pad2_ 3_and +* u4 p1_bar g1_bar net-_u10-pad2_ d_and +* u5 g0_bar net-_u20-pad2_ net-_u5-pad3_ d_and +* u6 p0_bar g0_bar net-_u6-pad3_ d_and +x10 net-_x10-pad1_ net-_x10-pad2_ net-_x10-pad3_ net-_u2-pad3_ net-_u1-pad10_ 4_OR +* u7 net-_u5-pad3_ net-_u6-pad3_ net-_u1-pad12_ d_nor +x11 net-_x11-pad1_ net-_x11-pad2_ net-_x11-pad3_ net-_u3-pad3_ net-_u9-pad1_ 4_OR +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u10-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u9 net-_u9-pad1_ net-_u1-pad9_ d_inverter +* u11 net-_u10-pad3_ net-_u1-pad11_ d_inverter +* u20 cn net-_u20-pad2_ d_inverter +* u1 g1_bar p1_bar g0_bar p0_bar g3_bar p3_bar net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ cn g2_bar p2_bar port +a1 [p3_bar g3_bar ] net-_u2-pad3_ u2 +a2 [p2_bar g2_bar ] net-_u3-pad3_ u3 +a3 [p1_bar g1_bar ] net-_u10-pad2_ u4 +a4 [g0_bar net-_u20-pad2_ ] net-_u5-pad3_ u5 +a5 [p0_bar g0_bar ] net-_u6-pad3_ u6 +a6 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u1-pad12_ u7 +a7 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u10-pad1_ u8 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a9 net-_u9-pad1_ net-_u1-pad9_ u9 +a10 net-_u10-pad3_ net-_u1-pad11_ u11 +a11 cn net-_u20-pad2_ u20 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 250e-03 10e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74S182/74S182.pro b/library/SubcircuitLibrary/74S182/74S182.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74S182/74S182.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74S182/74S182.sch b/library/SubcircuitLibrary/74S182/74S182.sch new file mode 100644 index 000000000..bc2b9796e --- /dev/null +++ b/library/SubcircuitLibrary/74S182/74S182.sch @@ -0,0 +1,733 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74S182-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4_OR X1 +U 1 1 685147D5 +P 4450 1200 +F 0 "X1" H 4600 1100 60 0000 C CNN +F 1 "4_OR" H 4600 1300 60 0000 C CNN +F 2 "" H 4450 1200 60 0000 C CNN +F 3 "" H 4450 1200 60 0000 C CNN + 1 4450 1200 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 6851483A +P 4500 2350 +F 0 "X4" H 4550 2300 60 0000 C CNN +F 1 "4_and" H 4600 2450 60 0000 C CNN +F 2 "" H 4500 2350 60 0000 C CNN +F 3 "" H 4500 2350 60 0000 C CNN + 1 4500 2350 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 68514869 +P 4500 2850 +F 0 "X5" H 4550 2800 60 0000 C CNN +F 1 "4_and" H 4600 2950 60 0000 C CNN +F 2 "" H 4500 2850 60 0000 C CNN +F 3 "" H 4500 2850 60 0000 C CNN + 1 4500 2850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 6851489F +P 4500 3350 +F 0 "X6" H 4600 3300 60 0000 C CNN +F 1 "3_and" H 4650 3500 60 0000 C CNN +F 2 "" H 4500 3350 60 0000 C CNN +F 3 "" H 4500 3350 60 0000 C CNN + 1 4500 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 685148D0 +P 4550 3750 +F 0 "U2" H 4550 3750 60 0000 C CNN +F 1 "d_and" H 4600 3850 60 0000 C CNN +F 2 "" H 4550 3750 60 0000 C CNN +F 3 "" H 4550 3750 60 0000 C CNN + 1 4550 3750 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 68514AF5 +P 4500 4700 +F 0 "X7" H 4550 4650 60 0000 C CNN +F 1 "4_and" H 4600 4800 60 0000 C CNN +F 2 "" H 4500 4700 60 0000 C CNN +F 3 "" H 4500 4700 60 0000 C CNN + 1 4500 4700 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X8 +U 1 1 68514AFB +P 4500 5200 +F 0 "X8" H 4550 5150 60 0000 C CNN +F 1 "4_and" H 4600 5300 60 0000 C CNN +F 2 "" H 4500 5200 60 0000 C CNN +F 3 "" H 4500 5200 60 0000 C CNN + 1 4500 5200 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X9 +U 1 1 68514B01 +P 4500 5700 +F 0 "X9" H 4600 5650 60 0000 C CNN +F 1 "3_and" H 4650 5850 60 0000 C CNN +F 2 "" H 4500 5700 60 0000 C CNN +F 3 "" H 4500 5700 60 0000 C CNN + 1 4500 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 68514B07 +P 4550 6100 +F 0 "U3" H 4550 6100 60 0000 C CNN +F 1 "d_and" H 4600 6200 60 0000 C CNN +F 2 "" H 4550 6100 60 0000 C CNN +F 3 "" H 4550 6100 60 0000 C CNN + 1 4550 6100 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 68514BBA +P 4450 7100 +F 0 "X2" H 4550 7050 60 0000 C CNN +F 1 "3_and" H 4600 7250 60 0000 C CNN +F 2 "" H 4450 7100 60 0000 C CNN +F 3 "" H 4450 7100 60 0000 C CNN + 1 4450 7100 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 68514C43 +P 4450 7600 +F 0 "X3" H 4550 7550 60 0000 C CNN +F 1 "3_and" H 4600 7750 60 0000 C CNN +F 2 "" H 4450 7600 60 0000 C CNN +F 3 "" H 4450 7600 60 0000 C CNN + 1 4450 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 68514C86 +P 4550 8050 +F 0 "U4" H 4550 8050 60 0000 C CNN +F 1 "d_and" H 4600 8150 60 0000 C CNN +F 2 "" H 4550 8050 60 0000 C CNN +F 3 "" H 4550 8050 60 0000 C CNN + 1 4550 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 68514D0F +P 4550 8900 +F 0 "U5" H 4550 8900 60 0000 C CNN +F 1 "d_and" H 4600 9000 60 0000 C CNN +F 2 "" H 4550 8900 60 0000 C CNN +F 3 "" H 4550 8900 60 0000 C CNN + 1 4550 8900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 68514D9A +P 4550 9300 +F 0 "U6" H 4550 9300 60 0000 C CNN +F 1 "d_and" H 4600 9400 60 0000 C CNN +F 2 "" H 4550 9300 60 0000 C CNN +F 3 "" H 4550 9300 60 0000 C CNN + 1 4550 9300 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X10 +U 1 1 68514E70 +P 6400 3000 +F 0 "X10" H 6550 2900 60 0000 C CNN +F 1 "4_OR" H 6550 3100 60 0000 C CNN +F 2 "" H 6400 3000 60 0000 C CNN +F 3 "" H 6400 3000 60 0000 C CNN + 1 6400 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 68515194 +P 6400 9000 +F 0 "U7" H 6400 9000 60 0000 C CNN +F 1 "d_nor" H 6450 9100 60 0000 C CNN +F 2 "" H 6400 9000 60 0000 C CNN +F 3 "" H 6400 9000 60 0000 C CNN + 1 6400 9000 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X11 +U 1 1 68515632 +P 6400 5200 +F 0 "X11" H 6550 5100 60 0000 C CNN +F 1 "4_OR" H 6550 5300 60 0000 C CNN +F 2 "" H 6400 5200 60 0000 C CNN +F 3 "" H 6400 5200 60 0000 C CNN + 1 6400 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U8 +U 1 1 685156A8 +P 6650 7300 +F 0 "U8" H 6650 7300 60 0000 C CNN +F 1 "d_or" H 6650 7400 60 0000 C CNN +F 2 "" H 6650 7300 60 0000 C CNN +F 3 "" H 6650 7300 60 0000 C CNN + 1 6650 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U10 +U 1 1 685156FD +P 7750 7700 +F 0 "U10" H 7750 7700 60 0000 C CNN +F 1 "d_or" H 7750 7800 60 0000 C CNN +F 2 "" H 7750 7700 60 0000 C CNN +F 3 "" H 7750 7700 60 0000 C CNN + 1 7750 7700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6851575A +P 7550 5200 +F 0 "U9" H 7550 5100 60 0000 C CNN +F 1 "d_inverter" H 7550 5350 60 0000 C CNN +F 2 "" H 7600 5150 60 0000 C CNN +F 3 "" H 7600 5150 60 0000 C CNN + 1 7550 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 6851589D +P 9100 7650 +F 0 "U11" H 9100 7550 60 0000 C CNN +F 1 "d_inverter" H 9100 7800 60 0000 C CNN +F 2 "" H 9150 7600 60 0000 C CNN +F 3 "" H 9150 7600 60 0000 C CNN + 1 9100 7650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 6851594F +P 3050 9800 +F 0 "U20" H 3050 9700 60 0000 C CNN +F 1 "d_inverter" H 3050 9950 60 0000 C CNN +F 2 "" H 3100 9750 60 0000 C CNN +F 3 "" H 3100 9750 60 0000 C CNN + 1 3050 9800 + 1 0 0 -1 +$EndComp +Text GLabel 2250 9800 0 60 Input ~ 0 +Cn +Text GLabel 2250 9200 0 60 Input ~ 0 +P0_bar +Text GLabel 2250 9450 0 60 Input ~ 0 +G0_bar +Text GLabel 2300 8150 0 60 Input ~ 0 +G1_bar +Text GLabel 2300 7950 0 60 Input ~ 0 +P1_bar +Text GLabel 2350 6250 0 60 Input ~ 0 +G2_bar +Text GLabel 2350 6000 0 60 Input ~ 0 +P2_bar +Text GLabel 2450 4050 0 60 Input ~ 0 +G3_bar +Wire Wire Line + 2250 9800 2750 9800 +Wire Wire Line + 3950 9800 3350 9800 +Wire Wire Line + 3950 4850 3950 9800 +Wire Wire Line + 3950 8900 4100 8900 +Wire Wire Line + 2250 9450 4050 9450 +Wire Wire Line + 4050 9450 4050 9300 +Wire Wire Line + 4050 9300 4100 9300 +Wire Wire Line + 2250 9200 4100 9200 +Wire Wire Line + 4100 8800 3850 8800 +Wire Wire Line + 3850 2500 3850 9450 +Connection ~ 3850 9450 +Wire Wire Line + 2300 8150 4050 8150 +Wire Wire Line + 4050 8150 4050 8050 +Wire Wire Line + 4050 8050 4100 8050 +Wire Wire Line + 2300 7950 4100 7950 +Wire Wire Line + 4100 7650 3850 7650 +Connection ~ 3850 8800 +Wire Wire Line + 4100 7550 3750 7550 +Wire Wire Line + 3750 2400 3750 8150 +Connection ~ 3750 8150 +Wire Wire Line + 4100 7450 3650 7450 +Wire Wire Line + 3650 7450 3650 9200 +Connection ~ 3650 9200 +Wire Wire Line + 3950 7150 4100 7150 +Connection ~ 3950 8900 +Wire Wire Line + 4100 7050 3850 7050 +Connection ~ 3850 7650 +Wire Wire Line + 4100 6950 3750 6950 +Connection ~ 3750 7550 +Wire Wire Line + 2350 6250 4000 6250 +Wire Wire Line + 4000 6250 4000 6100 +Wire Wire Line + 4000 6100 4100 6100 +Wire Wire Line + 2350 6000 4100 6000 +Wire Wire Line + 4150 5750 3750 5750 +Connection ~ 3750 6950 +Wire Wire Line + 4150 5650 3650 5650 +Wire Wire Line + 3650 2300 3650 6250 +Connection ~ 3650 6250 +Wire Wire Line + 4150 5550 3500 5550 +Wire Wire Line + 3500 1250 3500 7950 +Connection ~ 3500 7950 +Wire Wire Line + 4100 5350 3850 5350 +Connection ~ 3850 7050 +Wire Wire Line + 4100 5250 3750 5250 +Connection ~ 3750 5750 +Wire Wire Line + 4100 5150 3650 5150 +Connection ~ 3650 5650 +Wire Wire Line + 4100 5050 3400 5050 +Wire Wire Line + 3400 1350 3400 9200 +Connection ~ 3400 9200 +Wire Wire Line + 3950 4850 4100 4850 +Connection ~ 3950 7150 +Wire Wire Line + 3850 4750 4100 4750 +Connection ~ 3850 5350 +Wire Wire Line + 4100 4650 3750 4650 +Connection ~ 3750 5250 +Wire Wire Line + 4100 4550 3650 4550 +Connection ~ 3650 5150 +Wire Wire Line + 2450 4050 4000 4050 +Wire Wire Line + 4000 4050 4000 3750 +Wire Wire Line + 4000 3750 4100 3750 +Wire Wire Line + 3650 3400 4150 3400 +Connection ~ 3650 4550 +Wire Wire Line + 4150 3300 3200 3300 +Wire Wire Line + 3200 2200 3200 4050 +Connection ~ 3200 4050 +Wire Wire Line + 4150 3200 3100 3200 +Wire Wire Line + 3100 1150 3100 6000 +Connection ~ 3100 6000 +Wire Wire Line + 3750 3000 4100 3000 +Connection ~ 3750 4650 +Wire Wire Line + 4100 2900 3650 2900 +Connection ~ 3650 3400 +Wire Wire Line + 4100 2800 3200 2800 +Connection ~ 3200 3300 +Wire Wire Line + 3500 2700 4100 2700 +Connection ~ 3500 5550 +Wire Wire Line + 4100 2500 3850 2500 +Connection ~ 3850 4750 +Wire Wire Line + 4100 2400 3750 2400 +Connection ~ 3750 3000 +Wire Wire Line + 4100 2300 3650 2300 +Connection ~ 3650 2900 +Wire Wire Line + 4100 2200 3200 2200 +Connection ~ 3200 2800 +Wire Wire Line + 3400 1350 4100 1350 +Connection ~ 3400 5050 +Wire Wire Line + 3500 1250 4100 1250 +Connection ~ 3500 2700 +Wire Wire Line + 3100 1150 4100 1150 +Connection ~ 3100 3200 +Wire Wire Line + 4100 1050 3000 1050 +Wire Wire Line + 3000 1050 3000 3650 +Connection ~ 3000 3650 +Wire Wire Line + 5000 8850 5900 8850 +Wire Wire Line + 5900 8850 5900 8900 +Wire Wire Line + 5900 8900 5950 8900 +Wire Wire Line + 5000 9250 5000 9000 +Wire Wire Line + 5000 9000 5950 9000 +Wire Wire Line + 4950 7050 6200 7050 +Wire Wire Line + 6200 7050 6200 7200 +Wire Wire Line + 4950 7550 6200 7550 +Wire Wire Line + 6200 7550 6200 7300 +Wire Wire Line + 5000 8000 7300 8000 +Wire Wire Line + 7300 8000 7300 7700 +Wire Wire Line + 7100 7250 7300 7250 +Wire Wire Line + 7300 7250 7300 7600 +Wire Wire Line + 8200 7650 8800 7650 +Wire Wire Line + 5000 4700 6050 4700 +Wire Wire Line + 6050 4700 6050 5050 +Wire Wire Line + 5000 5200 5000 5150 +Wire Wire Line + 5000 5150 6050 5150 +Wire Wire Line + 5000 5650 5050 5650 +Wire Wire Line + 5050 5650 5050 5250 +Wire Wire Line + 5050 5250 6050 5250 +Wire Wire Line + 5000 6050 5150 6050 +Wire Wire Line + 5150 6050 5150 5350 +Wire Wire Line + 5150 5350 6050 5350 +Wire Wire Line + 6950 5200 7250 5200 +Wire Wire Line + 5000 3700 6050 3700 +Wire Wire Line + 6050 3700 6050 3150 +Wire Wire Line + 5000 3300 5950 3300 +Wire Wire Line + 5950 3300 5950 3050 +Wire Wire Line + 5950 3050 6050 3050 +Wire Wire Line + 5000 2850 5000 2950 +Wire Wire Line + 5000 2950 6050 2950 +Wire Wire Line + 5000 2350 6050 2350 +Wire Wire Line + 6050 2350 6050 2850 +$Comp +L PORT U1 +U 1 1 6851A559 +P 2600 8500 +F 0 "U1" H 2650 8600 30 0000 C CNN +F 1 "PORT" H 2600 8500 30 0000 C CNN +F 2 "" H 2600 8500 60 0000 C CNN +F 3 "" H 2600 8500 60 0000 C CNN + 1 2600 8500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 6851A8EA +P 2600 7550 +F 0 "U1" H 2650 7650 30 0000 C CNN +F 1 "PORT" H 2600 7550 30 0000 C CNN +F 2 "" H 2600 7550 60 0000 C CNN +F 3 "" H 2600 7550 60 0000 C CNN + 2 2600 7550 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 6851A9AF +P 3000 8900 +F 0 "U1" H 3050 9000 30 0000 C CNN +F 1 "PORT" H 3000 8900 30 0000 C CNN +F 2 "" H 3000 8900 60 0000 C CNN +F 3 "" H 3000 8900 60 0000 C CNN + 3 3000 8900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 6851AA0C +P 2700 8900 +F 0 "U1" H 2750 9000 30 0000 C CNN +F 1 "PORT" H 2700 8900 30 0000 C CNN +F 2 "" H 2700 8900 60 0000 C CNN +F 3 "" H 2700 8900 60 0000 C CNN + 4 2700 8900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 6851AAB3 +P 2750 4450 +F 0 "U1" H 2800 4550 30 0000 C CNN +F 1 "PORT" H 2750 4450 30 0000 C CNN +F 2 "" H 2750 4450 60 0000 C CNN +F 3 "" H 2750 4450 60 0000 C CNN + 5 2750 4450 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 6851AC68 +P 2750 3300 +F 0 "U1" H 2800 3400 30 0000 C CNN +F 1 "PORT" H 2750 3300 30 0000 C CNN +F 2 "" H 2750 3300 60 0000 C CNN +F 3 "" H 2750 3300 60 0000 C CNN + 6 2750 3300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 6851ADB1 +P 5950 1200 +F 0 "U1" H 6000 1300 30 0000 C CNN +F 1 "PORT" H 5950 1200 30 0000 C CNN +F 2 "" H 5950 1200 60 0000 C CNN +F 3 "" H 5950 1200 60 0000 C CNN + 7 5950 1200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 6851AEAF +P 8650 5200 +F 0 "U1" H 8700 5300 30 0000 C CNN +F 1 "PORT" H 8650 5200 30 0000 C CNN +F 2 "" H 8650 5200 60 0000 C CNN +F 3 "" H 8650 5200 60 0000 C CNN + 9 8650 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6851B080 +P 8100 3000 +F 0 "U1" H 8150 3100 30 0000 C CNN +F 1 "PORT" H 8100 3000 30 0000 C CNN +F 2 "" H 8100 3000 60 0000 C CNN +F 3 "" H 8100 3000 60 0000 C CNN + 10 8100 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6851B267 +P 10450 7650 +F 0 "U1" H 10500 7750 30 0000 C CNN +F 1 "PORT" H 10450 7650 30 0000 C CNN +F 2 "" H 10450 7650 60 0000 C CNN +F 3 "" H 10450 7650 60 0000 C CNN + 11 10450 7650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6851B415 +P 7750 8950 +F 0 "U1" H 7800 9050 30 0000 C CNN +F 1 "PORT" H 7750 8950 30 0000 C CNN +F 2 "" H 7750 8950 60 0000 C CNN +F 3 "" H 7750 8950 60 0000 C CNN + 12 7750 8950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6851B85C +P 2550 10250 +F 0 "U1" H 2600 10350 30 0000 C CNN +F 1 "PORT" H 2550 10250 30 0000 C CNN +F 2 "" H 2550 10250 60 0000 C CNN +F 3 "" H 2550 10250 60 0000 C CNN + 13 2550 10250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 6851C350 +P 2750 6650 +F 0 "U1" H 2800 6750 30 0000 C CNN +F 1 "PORT" H 2750 6650 30 0000 C CNN +F 2 "" H 2750 6650 60 0000 C CNN +F 3 "" H 2750 6650 60 0000 C CNN + 14 2750 6650 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 6851C41F +P 2700 5600 +F 0 "U1" H 2750 5700 30 0000 C CNN +F 1 "PORT" H 2700 5600 30 0000 C CNN +F 2 "" H 2700 5600 60 0000 C CNN +F 3 "" H 2700 5600 60 0000 C CNN + 15 2700 5600 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 1200 5700 1200 +Wire Wire Line + 6950 3000 7850 3000 +Wire Wire Line + 2750 3550 2750 3650 +Connection ~ 2750 3650 +Wire Wire Line + 2750 4200 2750 4050 +Connection ~ 2750 4050 +Wire Wire Line + 2700 5850 2700 6000 +Connection ~ 2700 6000 +Wire Wire Line + 2750 6400 2750 6250 +Connection ~ 2750 6250 +Wire Wire Line + 7850 5200 8400 5200 +Wire Wire Line + 2600 7800 2600 7950 +Connection ~ 2600 7950 +Wire Wire Line + 2600 8250 2600 8150 +Connection ~ 2600 8150 +Wire Wire Line + 2700 9150 2700 9200 +Connection ~ 2700 9200 +Wire Wire Line + 3000 9150 3000 9450 +Connection ~ 3000 9450 +Wire Wire Line + 2550 10000 2550 9800 +Connection ~ 2550 9800 +Wire Wire Line + 10200 7650 9400 7650 +Wire Wire Line + 6850 8950 7500 8950 +Wire Wire Line + 2450 3650 4100 3650 +Text GLabel 2450 3650 0 60 Input ~ 0 +P3_bar +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74S182/74S182.sub b/library/SubcircuitLibrary/74S182/74S182.sub new file mode 100644 index 000000000..d82544930 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/74S182.sub @@ -0,0 +1,64 @@ +* Subcircuit 74S182 +.subckt 74S182 g1_bar p1_bar g0_bar p0_bar g3_bar p3_bar net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ cn g2_bar p2_bar +* c:\fossee\esim\library\subcircuitlibrary\74s182\74s182.cir +.include 4_OR.sub +.include 4_and.sub +.include 3_and.sub +x1 p3_bar p2_bar p1_bar p0_bar net-_u1-pad7_ 4_OR +x4 g3_bar g2_bar g1_bar g0_bar net-_x10-pad1_ 4_and +x5 p1_bar g3_bar g2_bar g1_bar net-_x10-pad2_ 4_and +x6 p2_bar g3_bar g2_bar net-_x10-pad3_ 3_and +* u2 p3_bar g3_bar net-_u2-pad3_ d_and +x7 g2_bar g1_bar g0_bar net-_u20-pad2_ net-_x11-pad1_ 4_and +x8 p0_bar g2_bar g1_bar g0_bar net-_x11-pad2_ 4_and +x9 p1_bar g2_bar g1_bar net-_x11-pad3_ 3_and +* u3 p2_bar g2_bar net-_u3-pad3_ d_and +x2 g1_bar g0_bar net-_u20-pad2_ net-_u8-pad1_ 3_and +x3 p0_bar g1_bar g0_bar net-_u8-pad2_ 3_and +* u4 p1_bar g1_bar net-_u10-pad2_ d_and +* u5 g0_bar net-_u20-pad2_ net-_u5-pad3_ d_and +* u6 p0_bar g0_bar net-_u6-pad3_ d_and +x10 net-_x10-pad1_ net-_x10-pad2_ net-_x10-pad3_ net-_u2-pad3_ net-_u1-pad10_ 4_OR +* u7 net-_u5-pad3_ net-_u6-pad3_ net-_u1-pad12_ d_nor +x11 net-_x11-pad1_ net-_x11-pad2_ net-_x11-pad3_ net-_u3-pad3_ net-_u9-pad1_ 4_OR +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u10-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u9 net-_u9-pad1_ net-_u1-pad9_ d_inverter +* u11 net-_u10-pad3_ net-_u1-pad11_ d_inverter +* u20 cn net-_u20-pad2_ d_inverter +a1 [p3_bar g3_bar ] net-_u2-pad3_ u2 +a2 [p2_bar g2_bar ] net-_u3-pad3_ u3 +a3 [p1_bar g1_bar ] net-_u10-pad2_ u4 +a4 [g0_bar net-_u20-pad2_ ] net-_u5-pad3_ u5 +a5 [p0_bar g0_bar ] net-_u6-pad3_ u6 +a6 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u1-pad12_ u7 +a7 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u10-pad1_ u8 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a9 net-_u9-pad1_ net-_u1-pad9_ u9 +a10 net-_u10-pad3_ net-_u1-pad11_ u11 +a11 cn net-_u20-pad2_ u20 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74S182 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74S182/74S182_Previous_Values.xml b/library/SubcircuitLibrary/74S182/74S182_Previous_Values.xml new file mode 100644 index 000000000..724f2c757 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/74S182_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_andd_andd_andd_nord_ord_ord_inverterd_inverterd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmsms \ No newline at end of file diff --git a/library/SubcircuitLibrary/74S182/analysis b/library/SubcircuitLibrary/74S182/analysis new file mode 100644 index 000000000..6bbeaba60 --- /dev/null +++ b/library/SubcircuitLibrary/74S182/analysis @@ -0,0 +1 @@ +.tran 250e-03 10e-03 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC14560B/3_and-cache.lib b/library/SubcircuitLibrary/MC14560B/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC14560B/3_and.cir b/library/SubcircuitLibrary/MC14560B/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC14560B/3_and.cir.out b/library/SubcircuitLibrary/MC14560B/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC14560B/3_and.pro b/library/SubcircuitLibrary/MC14560B/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/MC14560B/3_and.sch b/library/SubcircuitLibrary/MC14560B/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC14560B/3_and.sub b/library/SubcircuitLibrary/MC14560B/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC14560B/3_and_Previous_Values.xml b/library/SubcircuitLibrary/MC14560B/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC14560B/4_and-cache.lib b/library/SubcircuitLibrary/MC14560B/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC14560B/4_and-rescue.lib b/library/SubcircuitLibrary/MC14560B/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC14560B/4_and.cir b/library/SubcircuitLibrary/MC14560B/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC14560B/4_and.cir.out b/library/SubcircuitLibrary/MC14560B/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC14560B/4_and.pro b/library/SubcircuitLibrary/MC14560B/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/MC14560B/4_and.sch b/library/SubcircuitLibrary/MC14560B/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC14560B/4_and.sub b/library/SubcircuitLibrary/MC14560B/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC14560B/4_and_Previous_Values.xml b/library/SubcircuitLibrary/MC14560B/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B-cache.lib b/library/SubcircuitLibrary/MC14560B/MC14560B-cache.lib new file mode 100644 index 000000000..680d7b47d --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/MC14560B-cache.lib @@ -0,0 +1,168 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B.cir b/library/SubcircuitLibrary/MC14560B/MC14560B.cir new file mode 100644 index 000000000..8eac4591d --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/MC14560B.cir @@ -0,0 +1,81 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14560B\MC14560B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/04/25 23:36:10 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U10-Pad1_ d_nand +U9 Net-_U1-Pad5_ Net-_U10-Pad1_ Net-_U17-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad6_ Net-_U10-Pad3_ d_and +U17 Net-_U17-Pad1_ Net-_U10-Pad3_ Net-_U17-Pad3_ d_nor +U2 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_nand +U7 Net-_U1-Pad3_ Net-_U2-Pad3_ Net-_U16-Pad1_ d_and +U8 Net-_U2-Pad3_ Net-_U1-Pad4_ Net-_U16-Pad2_ d_and +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nor +U70 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U14-Pad1_ d_nand +U5 Net-_U1-Pad1_ Net-_U14-Pad1_ Net-_U15-Pad1_ d_and +U6 Net-_U14-Pad1_ Net-_U1-Pad2_ Net-_U15-Pad2_ d_and +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor +U4 Net-_U1-Pad15_ Net-_U1-Pad14_ Net-_U11-Pad2_ d_nand +U11 Net-_U1-Pad15_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U12 Net-_U11-Pad2_ Net-_U1-Pad14_ Net-_U12-Pad3_ d_and +U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U18-Pad3_ d_nor +U13 Net-_U11-Pad2_ Net-_U13-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U26 Net-_U1-Pad7_ Net-_U18-Pad3_ Net-_U26-Pad3_ d_nand +U29 Net-_U1-Pad7_ Net-_U26-Pad3_ Net-_U29-Pad3_ d_and +U30 Net-_U26-Pad3_ Net-_U18-Pad3_ Net-_U30-Pad3_ d_and +U36 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U1-Pad13_ d_nor +U20 Net-_U18-Pad3_ Net-_U20-Pad2_ d_inverter +U19 Net-_U15-Pad3_ Net-_U19-Pad2_ d_inverter +U21 Net-_U16-Pad3_ Net-_U21-Pad2_ d_inverter +U27 Net-_U1-Pad7_ Net-_U20-Pad2_ Net-_U27-Pad3_ d_and +U25 Net-_U13-Pad2_ Net-_U25-Pad2_ d_inverter +U31 Net-_U27-Pad3_ Net-_U25-Pad2_ Net-_U31-Pad3_ d_nor +U34 Net-_U31-Pad3_ Net-_U19-Pad2_ Net-_U34-Pad3_ d_xor +U40 Net-_U34-Pad3_ Net-_U40-Pad2_ d_inverter +X3 Net-_U1-Pad7_ Net-_U20-Pad2_ Net-_U19-Pad2_ Net-_U32-Pad1_ 3_and +U23 Net-_U13-Pad2_ Net-_U19-Pad2_ Net-_U23-Pad3_ d_and +U24 Net-_U14-Pad2_ Net-_U24-Pad2_ d_inverter +U32 Net-_U32-Pad1_ Net-_U23-Pad3_ Net-_U32-Pad3_ d_nor +U37 Net-_U32-Pad3_ Net-_U24-Pad2_ Net-_U37-Pad3_ d_nor +U41 Net-_U37-Pad3_ Net-_U21-Pad2_ Net-_U41-Pad3_ d_xor +X1 Net-_U13-Pad2_ Net-_U19-Pad2_ Net-_U21-Pad2_ Net-_U28-Pad2_ 3_and +U22 Net-_U14-Pad2_ Net-_U21-Pad2_ Net-_U22-Pad3_ d_and +U28 Net-_U28-Pad1_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_nor +U33 Net-_U28-Pad3_ Net-_U22-Pad3_ Net-_U33-Pad3_ d_nor +X2 Net-_U1-Pad7_ Net-_U20-Pad2_ Net-_U19-Pad2_ Net-_U21-Pad2_ Net-_U28-Pad1_ 4_and +X5 Net-_U2-Pad3_ Net-_U33-Pad3_ Net-_U38-Pad3_ Net-_U44-Pad1_ 3_and +U35 Net-_U33-Pad3_ Net-_U2-Pad3_ Net-_U35-Pad3_ d_nand +U38 Net-_U35-Pad3_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_nand +X4 Net-_U33-Pad3_ Net-_U2-Pad3_ Net-_U10-Pad1_ Net-_U43-Pad1_ 3_and +U39 Net-_U38-Pad2_ Net-_U10-Pad1_ Net-_U39-Pad3_ d_and +U43 Net-_U43-Pad1_ Net-_U39-Pad3_ Net-_U43-Pad3_ d_nor +U42 Net-_U38-Pad3_ Net-_U17-Pad3_ Net-_U42-Pad3_ d_and +U44 Net-_U44-Pad1_ Net-_U42-Pad3_ Net-_U44-Pad3_ d_nor +U45 Net-_U44-Pad3_ Net-_U45-Pad2_ d_inverter +U46 Net-_U43-Pad3_ Net-_U46-Pad2_ d_inverter +X8 Net-_U34-Pad3_ Net-_U44-Pad3_ Net-_U46-Pad2_ Net-_U57-Pad1_ 3_and +U49 Net-_U40-Pad2_ Net-_U45-Pad2_ Net-_U49-Pad3_ d_and +U50 Net-_U41-Pad3_ Net-_U45-Pad2_ Net-_U50-Pad3_ d_and +U51 Net-_U40-Pad2_ Net-_U43-Pad3_ Net-_U51-Pad3_ d_and +U57 Net-_U57-Pad1_ Net-_U49-Pad3_ Net-_U57-Pad3_ d_nor +U58 Net-_U50-Pad3_ Net-_U51-Pad3_ Net-_U58-Pad3_ d_nor +U61 Net-_U57-Pad3_ Net-_U58-Pad3_ Net-_U1-Pad12_ d_nor +U47 Net-_U46-Pad2_ Net-_U44-Pad3_ Net-_U47-Pad3_ d_and +X7 Net-_U34-Pad3_ Net-_U41-Pad3_ Net-_U46-Pad2_ Net-_U55-Pad1_ 3_and +U55 Net-_U55-Pad1_ Net-_U47-Pad3_ Net-_U1-Pad9_ d_nor +U48 Net-_U40-Pad2_ Net-_U43-Pad3_ Net-_U48-Pad3_ d_and +X6 Net-_U34-Pad3_ Net-_U41-Pad3_ Net-_U45-Pad2_ Net-_U56-Pad1_ 3_and +U56 Net-_U56-Pad1_ Net-_U48-Pad3_ Net-_U56-Pad3_ d_nor +U60 Net-_U56-Pad3_ Net-_U1-Pad10_ d_inverter +U53 Net-_U34-Pad3_ Net-_U45-Pad2_ Net-_U53-Pad3_ d_and +U54 Net-_U40-Pad2_ Net-_U43-Pad3_ Net-_U54-Pad3_ d_and +U52 Net-_U41-Pad3_ Net-_U46-Pad2_ Net-_U52-Pad3_ d_and +U59 Net-_U52-Pad3_ Net-_U53-Pad3_ Net-_U59-Pad3_ d_nor +U62 Net-_U59-Pad3_ Net-_U54-Pad3_ Net-_U1-Pad11_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B.cir.out b/library/SubcircuitLibrary/MC14560B/MC14560B.cir.out new file mode 100644 index 000000000..fc3b725de --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/MC14560B.cir.out @@ -0,0 +1,270 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc14560b\mc14560b.cir + +.include 3_and.sub +.include 4_and.sub +* u3 net-_u1-pad5_ net-_u1-pad6_ net-_u10-pad1_ d_nand +* u9 net-_u1-pad5_ net-_u10-pad1_ net-_u17-pad1_ d_and +* u10 net-_u10-pad1_ net-_u1-pad6_ net-_u10-pad3_ d_and +* u17 net-_u17-pad1_ net-_u10-pad3_ net-_u17-pad3_ d_nor +* u2 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad3_ d_nand +* u7 net-_u1-pad3_ net-_u2-pad3_ net-_u16-pad1_ d_and +* u8 net-_u2-pad3_ net-_u1-pad4_ net-_u16-pad2_ d_and +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nor +* u70 net-_u1-pad1_ net-_u1-pad2_ net-_u14-pad1_ d_nand +* u5 net-_u1-pad1_ net-_u14-pad1_ net-_u15-pad1_ d_and +* u6 net-_u14-pad1_ net-_u1-pad2_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u4 net-_u1-pad15_ net-_u1-pad14_ net-_u11-pad2_ d_nand +* u11 net-_u1-pad15_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u11-pad2_ net-_u1-pad14_ net-_u12-pad3_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u18-pad3_ d_nor +* u13 net-_u11-pad2_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u26 net-_u1-pad7_ net-_u18-pad3_ net-_u26-pad3_ d_nand +* u29 net-_u1-pad7_ net-_u26-pad3_ net-_u29-pad3_ d_and +* u30 net-_u26-pad3_ net-_u18-pad3_ net-_u30-pad3_ d_and +* u36 net-_u29-pad3_ net-_u30-pad3_ net-_u1-pad13_ d_nor +* u20 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u19 net-_u15-pad3_ net-_u19-pad2_ d_inverter +* u21 net-_u16-pad3_ net-_u21-pad2_ d_inverter +* u27 net-_u1-pad7_ net-_u20-pad2_ net-_u27-pad3_ d_and +* u25 net-_u13-pad2_ net-_u25-pad2_ d_inverter +* u31 net-_u27-pad3_ net-_u25-pad2_ net-_u31-pad3_ d_nor +* u34 net-_u31-pad3_ net-_u19-pad2_ net-_u34-pad3_ d_xor +* u40 net-_u34-pad3_ net-_u40-pad2_ d_inverter +x3 net-_u1-pad7_ net-_u20-pad2_ net-_u19-pad2_ net-_u32-pad1_ 3_and +* u23 net-_u13-pad2_ net-_u19-pad2_ net-_u23-pad3_ d_and +* u24 net-_u14-pad2_ net-_u24-pad2_ d_inverter +* u32 net-_u32-pad1_ net-_u23-pad3_ net-_u32-pad3_ d_nor +* u37 net-_u32-pad3_ net-_u24-pad2_ net-_u37-pad3_ d_nor +* u41 net-_u37-pad3_ net-_u21-pad2_ net-_u41-pad3_ d_xor +x1 net-_u13-pad2_ net-_u19-pad2_ net-_u21-pad2_ net-_u28-pad2_ 3_and +* u22 net-_u14-pad2_ net-_u21-pad2_ net-_u22-pad3_ d_and +* u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nor +* u33 net-_u28-pad3_ net-_u22-pad3_ net-_u33-pad3_ d_nor +x2 net-_u1-pad7_ net-_u20-pad2_ net-_u19-pad2_ net-_u21-pad2_ net-_u28-pad1_ 4_and +x5 net-_u2-pad3_ net-_u33-pad3_ net-_u38-pad3_ net-_u44-pad1_ 3_and +* u35 net-_u33-pad3_ net-_u2-pad3_ net-_u35-pad3_ d_nand +* u38 net-_u35-pad3_ net-_u38-pad2_ net-_u38-pad3_ d_nand +x4 net-_u33-pad3_ net-_u2-pad3_ net-_u10-pad1_ net-_u43-pad1_ 3_and +* u39 net-_u38-pad2_ net-_u10-pad1_ net-_u39-pad3_ d_and +* u43 net-_u43-pad1_ net-_u39-pad3_ net-_u43-pad3_ d_nor +* u42 net-_u38-pad3_ net-_u17-pad3_ net-_u42-pad3_ d_and +* u44 net-_u44-pad1_ net-_u42-pad3_ net-_u44-pad3_ d_nor +* u45 net-_u44-pad3_ net-_u45-pad2_ d_inverter +* u46 net-_u43-pad3_ net-_u46-pad2_ d_inverter +x8 net-_u34-pad3_ net-_u44-pad3_ net-_u46-pad2_ net-_u57-pad1_ 3_and +* u49 net-_u40-pad2_ net-_u45-pad2_ net-_u49-pad3_ d_and +* u50 net-_u41-pad3_ net-_u45-pad2_ net-_u50-pad3_ d_and +* u51 net-_u40-pad2_ net-_u43-pad3_ net-_u51-pad3_ d_and +* u57 net-_u57-pad1_ net-_u49-pad3_ net-_u57-pad3_ d_nor +* u58 net-_u50-pad3_ net-_u51-pad3_ net-_u58-pad3_ d_nor +* u61 net-_u57-pad3_ net-_u58-pad3_ net-_u1-pad12_ d_nor +* u47 net-_u46-pad2_ net-_u44-pad3_ net-_u47-pad3_ d_and +x7 net-_u34-pad3_ net-_u41-pad3_ net-_u46-pad2_ net-_u55-pad1_ 3_and +* u55 net-_u55-pad1_ net-_u47-pad3_ net-_u1-pad9_ d_nor +* u48 net-_u40-pad2_ net-_u43-pad3_ net-_u48-pad3_ d_and +x6 net-_u34-pad3_ net-_u41-pad3_ net-_u45-pad2_ net-_u56-pad1_ 3_and +* u56 net-_u56-pad1_ net-_u48-pad3_ net-_u56-pad3_ d_nor +* u60 net-_u56-pad3_ net-_u1-pad10_ d_inverter +* u53 net-_u34-pad3_ net-_u45-pad2_ net-_u53-pad3_ d_and +* u54 net-_u40-pad2_ net-_u43-pad3_ net-_u54-pad3_ d_and +* u52 net-_u41-pad3_ net-_u46-pad2_ net-_u52-pad3_ d_and +* u59 net-_u52-pad3_ net-_u53-pad3_ net-_u59-pad3_ d_nor +* u62 net-_u59-pad3_ net-_u54-pad3_ net-_u1-pad11_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port +a1 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u10-pad1_ u3 +a2 [net-_u1-pad5_ net-_u10-pad1_ ] net-_u17-pad1_ u9 +a3 [net-_u10-pad1_ net-_u1-pad6_ ] net-_u10-pad3_ u10 +a4 [net-_u17-pad1_ net-_u10-pad3_ ] net-_u17-pad3_ u17 +a5 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +a6 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u16-pad1_ u7 +a7 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u16-pad2_ u8 +a8 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a9 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u14-pad1_ u70 +a10 [net-_u1-pad1_ net-_u14-pad1_ ] net-_u15-pad1_ u5 +a11 [net-_u14-pad1_ net-_u1-pad2_ ] net-_u15-pad2_ u6 +a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a13 [net-_u1-pad15_ net-_u1-pad14_ ] net-_u11-pad2_ u4 +a14 [net-_u1-pad15_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a15 [net-_u11-pad2_ net-_u1-pad14_ ] net-_u12-pad3_ u12 +a16 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u18-pad3_ u18 +a17 net-_u11-pad2_ net-_u13-pad2_ u13 +a18 net-_u14-pad1_ net-_u14-pad2_ u14 +a19 [net-_u1-pad7_ net-_u18-pad3_ ] net-_u26-pad3_ u26 +a20 [net-_u1-pad7_ net-_u26-pad3_ ] net-_u29-pad3_ u29 +a21 [net-_u26-pad3_ net-_u18-pad3_ ] net-_u30-pad3_ u30 +a22 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u1-pad13_ u36 +a23 net-_u18-pad3_ net-_u20-pad2_ u20 +a24 net-_u15-pad3_ net-_u19-pad2_ u19 +a25 net-_u16-pad3_ net-_u21-pad2_ u21 +a26 [net-_u1-pad7_ net-_u20-pad2_ ] net-_u27-pad3_ u27 +a27 net-_u13-pad2_ net-_u25-pad2_ u25 +a28 [net-_u27-pad3_ net-_u25-pad2_ ] net-_u31-pad3_ u31 +a29 [net-_u31-pad3_ net-_u19-pad2_ ] net-_u34-pad3_ u34 +a30 net-_u34-pad3_ net-_u40-pad2_ u40 +a31 [net-_u13-pad2_ net-_u19-pad2_ ] net-_u23-pad3_ u23 +a32 net-_u14-pad2_ net-_u24-pad2_ u24 +a33 [net-_u32-pad1_ net-_u23-pad3_ ] net-_u32-pad3_ u32 +a34 [net-_u32-pad3_ net-_u24-pad2_ ] net-_u37-pad3_ u37 +a35 [net-_u37-pad3_ net-_u21-pad2_ ] net-_u41-pad3_ u41 +a36 [net-_u14-pad2_ net-_u21-pad2_ ] net-_u22-pad3_ u22 +a37 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a38 [net-_u28-pad3_ net-_u22-pad3_ ] net-_u33-pad3_ u33 +a39 [net-_u33-pad3_ net-_u2-pad3_ ] net-_u35-pad3_ u35 +a40 [net-_u35-pad3_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a41 [net-_u38-pad2_ net-_u10-pad1_ ] net-_u39-pad3_ u39 +a42 [net-_u43-pad1_ net-_u39-pad3_ ] net-_u43-pad3_ u43 +a43 [net-_u38-pad3_ net-_u17-pad3_ ] net-_u42-pad3_ u42 +a44 [net-_u44-pad1_ net-_u42-pad3_ ] net-_u44-pad3_ u44 +a45 net-_u44-pad3_ net-_u45-pad2_ u45 +a46 net-_u43-pad3_ net-_u46-pad2_ u46 +a47 [net-_u40-pad2_ net-_u45-pad2_ ] net-_u49-pad3_ u49 +a48 [net-_u41-pad3_ net-_u45-pad2_ ] net-_u50-pad3_ u50 +a49 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u51-pad3_ u51 +a50 [net-_u57-pad1_ net-_u49-pad3_ ] net-_u57-pad3_ u57 +a51 [net-_u50-pad3_ net-_u51-pad3_ ] net-_u58-pad3_ u58 +a52 [net-_u57-pad3_ net-_u58-pad3_ ] net-_u1-pad12_ u61 +a53 [net-_u46-pad2_ net-_u44-pad3_ ] net-_u47-pad3_ u47 +a54 [net-_u55-pad1_ net-_u47-pad3_ ] net-_u1-pad9_ u55 +a55 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u48-pad3_ u48 +a56 [net-_u56-pad1_ net-_u48-pad3_ ] net-_u56-pad3_ u56 +a57 net-_u56-pad3_ net-_u1-pad10_ u60 +a58 [net-_u34-pad3_ net-_u45-pad2_ ] net-_u53-pad3_ u53 +a59 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u54-pad3_ u54 +a60 [net-_u41-pad3_ net-_u46-pad2_ ] net-_u52-pad3_ u52 +a61 [net-_u52-pad3_ net-_u53-pad3_ ] net-_u59-pad3_ u59 +a62 [net-_u59-pad3_ net-_u54-pad3_ ] net-_u1-pad11_ u62 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u70 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u34 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u41 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u57 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u58 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u61 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u55 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u56 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u59 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u62 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 250e-03 10e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B.pro b/library/SubcircuitLibrary/MC14560B/MC14560B.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/MC14560B.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B.sch b/library/SubcircuitLibrary/MC14560B/MC14560B.sch new file mode 100644 index 000000000..a94a23bab --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/MC14560B.sch @@ -0,0 +1,1571 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:nbcd_adder-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U3 +U 1 1 6868181D +P 12300 11000 +F 0 "U3" H 12300 11000 60 0000 C CNN +F 1 "d_nand" H 12350 11100 60 0000 C CNN +F 2 "" H 12300 11000 60 0000 C CNN +F 3 "" H 12300 11000 60 0000 C CNN + 1 12300 11000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 6868181E +P 13400 10650 +F 0 "U9" H 13400 10650 60 0000 C CNN +F 1 "d_and" H 13450 10750 60 0000 C CNN +F 2 "" H 13400 10650 60 0000 C CNN +F 3 "" H 13400 10650 60 0000 C CNN + 1 13400 10650 + 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CNN + 1 19350 12400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U38 +U 1 1 68681848 +P 19800 12850 +F 0 "U38" H 19800 12850 60 0000 C CNN +F 1 "d_nand" H 19850 12950 60 0000 C CNN +F 2 "" H 19800 12850 60 0000 C CNN +F 3 "" H 19800 12850 60 0000 C CNN + 1 19800 12850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 68681849 +P 19950 13700 +F 0 "X4" H 20050 13650 60 0000 C CNN +F 1 "3_and" H 20100 13850 60 0000 C CNN +F 2 "" H 19950 13700 60 0000 C CNN +F 3 "" H 19950 13700 60 0000 C CNN + 1 19950 13700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U39 +U 1 1 6868184A +P 20050 14200 +F 0 "U39" H 20050 14200 60 0000 C CNN +F 1 "d_and" H 20100 14300 60 0000 C CNN +F 2 "" H 20050 14200 60 0000 C CNN +F 3 "" H 20050 14200 60 0000 C CNN + 1 20050 14200 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U43 +U 1 1 6868184B +P 21150 13900 +F 0 "U43" H 21150 13900 60 0000 C CNN +F 1 "d_nor" H 21200 14000 60 0000 C CNN +F 2 "" H 21150 13900 60 0000 C CNN +F 3 "" H 21150 13900 60 0000 C CNN + 1 21150 13900 + 1 0 0 -1 +$EndComp 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CNN +F 1 "d_nor" H 27500 6400 60 0000 C CNN +F 2 "" H 27450 6300 60 0000 C CNN +F 3 "" H 27450 6300 60 0000 C CNN + 1 27450 6300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U58 +U 1 1 68681855 +P 27450 7000 +F 0 "U58" H 27450 7000 60 0000 C CNN +F 1 "d_nor" H 27500 7100 60 0000 C CNN +F 2 "" H 27450 7000 60 0000 C CNN +F 3 "" H 27450 7000 60 0000 C CNN + 1 27450 7000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U61 +U 1 1 68681856 +P 28550 6650 +F 0 "U61" H 28550 6650 60 0000 C CNN +F 1 "d_nor" H 28600 6750 60 0000 C CNN +F 2 "" H 28550 6650 60 0000 C CNN +F 3 "" H 28550 6650 60 0000 C CNN + 1 28550 6650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U47 +U 1 1 68681857 +P 26100 12250 +F 0 "U47" H 26100 12250 60 0000 C CNN +F 1 "d_and" H 26150 12350 60 0000 C CNN +F 2 "" H 26100 12250 60 0000 C CNN +F 3 "" H 26100 12250 60 0000 C CNN + 1 26100 12250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X7 +U 1 1 68681858 +P 26100 11750 +F 0 "X7" H 26200 11700 60 0000 C CNN +F 1 "3_and" H 26250 11900 60 0000 C CNN +F 2 "" H 26100 11750 60 0000 C CNN +F 3 "" H 26100 11750 60 0000 C CNN + 1 26100 11750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U55 +U 1 1 68681859 +P 27200 12000 +F 0 "U55" H 27200 12000 60 0000 C CNN +F 1 "d_nor" H 27250 12100 60 0000 C CNN +F 2 "" H 27200 12000 60 0000 C CNN +F 3 "" H 27200 12000 60 0000 C CNN + 1 27200 12000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U48 +U 1 1 6868185A +P 26200 10750 +F 0 "U48" H 26200 10750 60 0000 C CNN +F 1 "d_and" H 26250 10850 60 0000 C CNN +F 2 "" H 26200 10750 60 0000 C CNN +F 3 "" H 26200 10750 60 0000 C CNN + 1 26200 10750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 6868185B +P 26100 10350 +F 0 "X6" H 26200 10300 60 0000 C CNN +F 1 "3_and" H 26250 10500 60 0000 C CNN +F 2 "" H 26100 10350 60 0000 C CNN +F 3 "" H 26100 10350 60 0000 C CNN + 1 26100 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U56 +U 1 1 6868185C +P 27300 10550 +F 0 "U56" H 27300 10550 60 0000 C CNN +F 1 "d_nor" H 27350 10650 60 0000 C CNN +F 2 "" H 27300 10550 60 0000 C CNN +F 3 "" H 27300 10550 60 0000 C CNN + 1 27300 10550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U60 +U 1 1 6868185D +P 28450 10500 +F 0 "U60" H 28450 10400 60 0000 C CNN +F 1 "d_inverter" H 28450 10650 60 0000 C CNN +F 2 "" H 28500 10450 60 0000 C CNN +F 3 "" H 28500 10450 60 0000 C CNN + 1 28450 10500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U53 +U 1 1 6868185E +P 26350 8750 +F 0 "U53" H 26350 8750 60 0000 C CNN +F 1 "d_and" H 26400 8850 60 0000 C CNN +F 2 "" H 26350 8750 60 0000 C CNN +F 3 "" H 26350 8750 60 0000 C CNN + 1 26350 8750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U54 +U 1 1 6868185F +P 26350 9200 +F 0 "U54" H 26350 9200 60 0000 C CNN +F 1 "d_and" H 26400 9300 60 0000 C CNN +F 2 "" H 26350 9200 60 0000 C CNN +F 3 "" H 26350 9200 60 0000 C CNN + 1 26350 9200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U52 +U 1 1 68681860 +P 26350 8350 +F 0 "U52" H 26350 8350 60 0000 C CNN +F 1 "d_and" H 26400 8450 60 0000 C CNN +F 2 "" H 26350 8350 60 0000 C CNN +F 3 "" H 26350 8350 60 0000 C CNN + 1 26350 8350 + 1 0 0 -1 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0000 C CNN +F 1 "PORT" H 8750 8350 30 0000 C CNN +F 2 "" H 8750 8350 60 0000 C CNN +F 3 "" H 8750 8350 60 0000 C CNN + 2 8750 8350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68689117 +P 11050 9450 +F 0 "U1" H 11100 9550 30 0000 C CNN +F 1 "PORT" H 11050 9450 30 0000 C CNN +F 2 "" H 11050 9450 60 0000 C CNN +F 3 "" H 11050 9450 60 0000 C CNN + 3 11050 9450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68689257 +P 8050 10150 +F 0 "U1" H 8100 10250 30 0000 C CNN +F 1 "PORT" H 8050 10150 30 0000 C CNN +F 2 "" H 8050 10150 60 0000 C CNN +F 3 "" H 8050 10150 60 0000 C CNN + 4 8050 10150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68689432 +P 8150 10550 +F 0 "U1" H 8200 10650 30 0000 C CNN +F 1 "PORT" H 8150 10550 30 0000 C CNN +F 2 "" H 8150 10550 60 0000 C CNN +F 3 "" H 8150 10550 60 0000 C CNN + 5 8150 10550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68689509 +P 8200 11250 +F 0 "U1" H 8250 11350 30 0000 C CNN +F 1 "PORT" H 8200 11250 30 0000 C CNN +F 2 "" H 8200 11250 60 0000 C CNN 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MC14560B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ +* c:\fossee\esim\library\subcircuitlibrary\mc14560b\mc14560b.cir +.include 3_and.sub +.include 4_and.sub +* u3 net-_u1-pad5_ net-_u1-pad6_ net-_u10-pad1_ d_nand +* u9 net-_u1-pad5_ net-_u10-pad1_ net-_u17-pad1_ d_and +* u10 net-_u10-pad1_ net-_u1-pad6_ net-_u10-pad3_ d_and +* u17 net-_u17-pad1_ net-_u10-pad3_ net-_u17-pad3_ d_nor +* u2 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad3_ d_nand +* u7 net-_u1-pad3_ net-_u2-pad3_ net-_u16-pad1_ d_and +* u8 net-_u2-pad3_ net-_u1-pad4_ net-_u16-pad2_ d_and +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nor +* u70 net-_u1-pad1_ net-_u1-pad2_ net-_u14-pad1_ d_nand +* u5 net-_u1-pad1_ net-_u14-pad1_ net-_u15-pad1_ d_and +* u6 net-_u14-pad1_ net-_u1-pad2_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u4 net-_u1-pad15_ net-_u1-pad14_ net-_u11-pad2_ d_nand +* u11 net-_u1-pad15_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u11-pad2_ net-_u1-pad14_ net-_u12-pad3_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u18-pad3_ d_nor +* u13 net-_u11-pad2_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u26 net-_u1-pad7_ net-_u18-pad3_ net-_u26-pad3_ d_nand +* u29 net-_u1-pad7_ net-_u26-pad3_ net-_u29-pad3_ d_and +* u30 net-_u26-pad3_ net-_u18-pad3_ net-_u30-pad3_ d_and +* u36 net-_u29-pad3_ net-_u30-pad3_ net-_u1-pad13_ d_nor +* u20 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u19 net-_u15-pad3_ net-_u19-pad2_ d_inverter +* u21 net-_u16-pad3_ net-_u21-pad2_ d_inverter +* u27 net-_u1-pad7_ net-_u20-pad2_ net-_u27-pad3_ d_and +* u25 net-_u13-pad2_ net-_u25-pad2_ d_inverter +* u31 net-_u27-pad3_ net-_u25-pad2_ net-_u31-pad3_ d_nor +* u34 net-_u31-pad3_ net-_u19-pad2_ net-_u34-pad3_ d_xor +* u40 net-_u34-pad3_ net-_u40-pad2_ d_inverter +x3 net-_u1-pad7_ net-_u20-pad2_ net-_u19-pad2_ net-_u32-pad1_ 3_and +* u23 net-_u13-pad2_ net-_u19-pad2_ net-_u23-pad3_ d_and +* u24 net-_u14-pad2_ net-_u24-pad2_ d_inverter +* u32 net-_u32-pad1_ net-_u23-pad3_ net-_u32-pad3_ d_nor +* u37 net-_u32-pad3_ net-_u24-pad2_ net-_u37-pad3_ d_nor +* u41 net-_u37-pad3_ net-_u21-pad2_ net-_u41-pad3_ d_xor +x1 net-_u13-pad2_ net-_u19-pad2_ net-_u21-pad2_ net-_u28-pad2_ 3_and +* u22 net-_u14-pad2_ net-_u21-pad2_ net-_u22-pad3_ d_and +* u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nor +* u33 net-_u28-pad3_ net-_u22-pad3_ net-_u33-pad3_ d_nor +x2 net-_u1-pad7_ net-_u20-pad2_ net-_u19-pad2_ net-_u21-pad2_ net-_u28-pad1_ 4_and +x5 net-_u2-pad3_ net-_u33-pad3_ net-_u38-pad3_ net-_u44-pad1_ 3_and +* u35 net-_u33-pad3_ net-_u2-pad3_ net-_u35-pad3_ d_nand +* u38 net-_u35-pad3_ net-_u38-pad2_ net-_u38-pad3_ d_nand +x4 net-_u33-pad3_ net-_u2-pad3_ net-_u10-pad1_ net-_u43-pad1_ 3_and +* u39 net-_u38-pad2_ net-_u10-pad1_ net-_u39-pad3_ d_and +* u43 net-_u43-pad1_ net-_u39-pad3_ net-_u43-pad3_ d_nor +* u42 net-_u38-pad3_ net-_u17-pad3_ net-_u42-pad3_ d_and +* u44 net-_u44-pad1_ net-_u42-pad3_ net-_u44-pad3_ d_nor +* u45 net-_u44-pad3_ net-_u45-pad2_ d_inverter +* u46 net-_u43-pad3_ net-_u46-pad2_ d_inverter +x8 net-_u34-pad3_ net-_u44-pad3_ net-_u46-pad2_ net-_u57-pad1_ 3_and +* u49 net-_u40-pad2_ net-_u45-pad2_ net-_u49-pad3_ d_and +* u50 net-_u41-pad3_ net-_u45-pad2_ net-_u50-pad3_ d_and +* u51 net-_u40-pad2_ net-_u43-pad3_ net-_u51-pad3_ d_and +* u57 net-_u57-pad1_ net-_u49-pad3_ net-_u57-pad3_ d_nor +* u58 net-_u50-pad3_ net-_u51-pad3_ net-_u58-pad3_ d_nor +* u61 net-_u57-pad3_ net-_u58-pad3_ net-_u1-pad12_ d_nor +* u47 net-_u46-pad2_ net-_u44-pad3_ net-_u47-pad3_ d_and +x7 net-_u34-pad3_ net-_u41-pad3_ net-_u46-pad2_ net-_u55-pad1_ 3_and +* u55 net-_u55-pad1_ net-_u47-pad3_ net-_u1-pad9_ d_nor +* u48 net-_u40-pad2_ net-_u43-pad3_ net-_u48-pad3_ d_and +x6 net-_u34-pad3_ net-_u41-pad3_ net-_u45-pad2_ net-_u56-pad1_ 3_and +* u56 net-_u56-pad1_ net-_u48-pad3_ net-_u56-pad3_ d_nor +* u60 net-_u56-pad3_ net-_u1-pad10_ d_inverter +* u53 net-_u34-pad3_ net-_u45-pad2_ net-_u53-pad3_ d_and +* u54 net-_u40-pad2_ net-_u43-pad3_ net-_u54-pad3_ d_and +* u52 net-_u41-pad3_ net-_u46-pad2_ net-_u52-pad3_ d_and +* u59 net-_u52-pad3_ net-_u53-pad3_ net-_u59-pad3_ d_nor +* u62 net-_u59-pad3_ net-_u54-pad3_ net-_u1-pad11_ d_nor +a1 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u10-pad1_ u3 +a2 [net-_u1-pad5_ net-_u10-pad1_ ] net-_u17-pad1_ u9 +a3 [net-_u10-pad1_ net-_u1-pad6_ ] net-_u10-pad3_ u10 +a4 [net-_u17-pad1_ net-_u10-pad3_ ] net-_u17-pad3_ u17 +a5 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +a6 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u16-pad1_ u7 +a7 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u16-pad2_ u8 +a8 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a9 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u14-pad1_ u70 +a10 [net-_u1-pad1_ net-_u14-pad1_ ] net-_u15-pad1_ u5 +a11 [net-_u14-pad1_ net-_u1-pad2_ ] net-_u15-pad2_ u6 +a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a13 [net-_u1-pad15_ net-_u1-pad14_ ] net-_u11-pad2_ u4 +a14 [net-_u1-pad15_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a15 [net-_u11-pad2_ net-_u1-pad14_ ] net-_u12-pad3_ u12 +a16 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u18-pad3_ u18 +a17 net-_u11-pad2_ net-_u13-pad2_ u13 +a18 net-_u14-pad1_ net-_u14-pad2_ u14 +a19 [net-_u1-pad7_ net-_u18-pad3_ ] net-_u26-pad3_ u26 +a20 [net-_u1-pad7_ net-_u26-pad3_ ] net-_u29-pad3_ u29 +a21 [net-_u26-pad3_ net-_u18-pad3_ ] net-_u30-pad3_ u30 +a22 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u1-pad13_ u36 +a23 net-_u18-pad3_ net-_u20-pad2_ u20 +a24 net-_u15-pad3_ net-_u19-pad2_ u19 +a25 net-_u16-pad3_ net-_u21-pad2_ u21 +a26 [net-_u1-pad7_ net-_u20-pad2_ ] net-_u27-pad3_ u27 +a27 net-_u13-pad2_ net-_u25-pad2_ u25 +a28 [net-_u27-pad3_ net-_u25-pad2_ ] net-_u31-pad3_ u31 +a29 [net-_u31-pad3_ net-_u19-pad2_ ] net-_u34-pad3_ u34 +a30 net-_u34-pad3_ net-_u40-pad2_ u40 +a31 [net-_u13-pad2_ net-_u19-pad2_ ] net-_u23-pad3_ u23 +a32 net-_u14-pad2_ net-_u24-pad2_ u24 +a33 [net-_u32-pad1_ net-_u23-pad3_ ] net-_u32-pad3_ u32 +a34 [net-_u32-pad3_ net-_u24-pad2_ ] net-_u37-pad3_ u37 +a35 [net-_u37-pad3_ net-_u21-pad2_ ] net-_u41-pad3_ u41 +a36 [net-_u14-pad2_ net-_u21-pad2_ ] net-_u22-pad3_ u22 +a37 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a38 [net-_u28-pad3_ net-_u22-pad3_ ] net-_u33-pad3_ u33 +a39 [net-_u33-pad3_ net-_u2-pad3_ ] net-_u35-pad3_ u35 +a40 [net-_u35-pad3_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a41 [net-_u38-pad2_ net-_u10-pad1_ ] net-_u39-pad3_ u39 +a42 [net-_u43-pad1_ net-_u39-pad3_ ] net-_u43-pad3_ u43 +a43 [net-_u38-pad3_ net-_u17-pad3_ ] net-_u42-pad3_ u42 +a44 [net-_u44-pad1_ net-_u42-pad3_ ] net-_u44-pad3_ u44 +a45 net-_u44-pad3_ net-_u45-pad2_ u45 +a46 net-_u43-pad3_ net-_u46-pad2_ u46 +a47 [net-_u40-pad2_ net-_u45-pad2_ ] net-_u49-pad3_ u49 +a48 [net-_u41-pad3_ net-_u45-pad2_ ] net-_u50-pad3_ u50 +a49 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u51-pad3_ u51 +a50 [net-_u57-pad1_ net-_u49-pad3_ ] net-_u57-pad3_ u57 +a51 [net-_u50-pad3_ net-_u51-pad3_ ] net-_u58-pad3_ u58 +a52 [net-_u57-pad3_ net-_u58-pad3_ ] net-_u1-pad12_ u61 +a53 [net-_u46-pad2_ net-_u44-pad3_ ] net-_u47-pad3_ u47 +a54 [net-_u55-pad1_ net-_u47-pad3_ ] net-_u1-pad9_ u55 +a55 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u48-pad3_ u48 +a56 [net-_u56-pad1_ net-_u48-pad3_ ] net-_u56-pad3_ u56 +a57 net-_u56-pad3_ net-_u1-pad10_ u60 +a58 [net-_u34-pad3_ net-_u45-pad2_ ] net-_u53-pad3_ u53 +a59 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u54-pad3_ u54 +a60 [net-_u41-pad3_ net-_u46-pad2_ ] net-_u52-pad3_ u52 +a61 [net-_u52-pad3_ net-_u53-pad3_ ] net-_u59-pad3_ u59 +a62 [net-_u59-pad3_ net-_u54-pad3_ ] net-_u1-pad11_ u62 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u70 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u34 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u41 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u57 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u58 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u61 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u55 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u56 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u59 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u62 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends MC14560B \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B_Previous_Values.xml b/library/SubcircuitLibrary/MC14560B/MC14560B_Previous_Values.xml new file mode 100644 index 000000000..8e2e40529 --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/MC14560B_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecd_nandd_andd_andd_nord_nandd_andd_andd_nord_nandd_andd_andd_nord_nandd_andd_andd_nord_inverterd_inverterd_nandd_andd_andd_nord_inverterd_inverterd_inverterd_andd_inverterd_nord_xord_inverterd_andd_inverterd_nord_nord_xord_andd_nord_nord_nandd_nandd_andd_nord_andd_nord_inverterd_inverterd_andd_andd_andd_nord_nord_nord_andd_nord_andd_nord_inverterd_andd_andd_andd_nord_norC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC14560B/analysis b/library/SubcircuitLibrary/MC14560B/analysis new file mode 100644 index 000000000..0a6c83b5a --- /dev/null +++ b/library/SubcircuitLibrary/MC14560B/analysis @@ -0,0 +1 @@ +.tran 250e-03 10e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58-cache.lib b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58-cache.lib new file mode 100644 index 000000000..c743d042c --- /dev/null +++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir new file mode 100644 index 000000000..bcc97dfc0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74AUP1G58\SN74AUP1G58.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 20:55:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U7 Net-_U1-Pad3_ Net-_U4-Pad1_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad6_ Net-_U3-Pad2_ d_inverter +U4 Net-_U4-Pad1_ Net-_U3-Pad2_ Net-_U4-Pad3_ d_and +U5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U5-Pad3_ d_nor +U6 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad4_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir.out b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir.out new file mode 100644 index 000000000..9f7fa54fe --- /dev/null +++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir.out @@ -0,0 +1,36 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74aup1g58\sn74aup1g58.cir + +* u7 net-_u1-pad3_ net-_u4-pad1_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad6_ net-_u3-pad2_ d_inverter +* u4 net-_u4-pad1_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 net-_u2-pad2_ net-_u3-pad2_ net-_u5-pad3_ d_nor +* u6 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad4_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ port +a1 net-_u1-pad3_ net-_u4-pad1_ u7 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad6_ net-_u3-pad2_ u3 +a4 [net-_u4-pad1_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a5 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad4_ u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 250e-03 10e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.pro b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sch b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sch new file mode 100644 index 000000000..8b1d44e3f --- /dev/null +++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sch @@ -0,0 +1,199 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U7 +U 1 1 685AC144 +P 4800 3050 +F 0 "U7" H 4800 2950 60 0000 C CNN +F 1 "d_inverter" H 4800 3200 60 0000 C CNN +F 2 "" H 4850 3000 60 0000 C CNN +F 3 "" H 4850 3000 60 0000 C CNN + 1 4800 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 685AC16D +P 4800 3700 +F 0 "U2" H 4800 3600 60 0000 C CNN +F 1 "d_inverter" H 4800 3850 60 0000 C CNN +F 2 "" H 4850 3650 60 0000 C CNN +F 3 "" H 4850 3650 60 0000 C CNN + 1 4800 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 685AC19E +P 4800 4400 +F 0 "U3" H 4800 4300 60 0000 C CNN +F 1 "d_inverter" H 4800 4550 60 0000 C CNN +F 2 "" H 4850 4350 60 0000 C CNN +F 3 "" H 4850 4350 60 0000 C CNN + 1 4800 4400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 685AC1E0 +P 6900 3350 +F 0 "U4" H 6900 3350 60 0000 C CNN +F 1 "d_and" H 6950 3450 60 0000 C CNN +F 2 "" H 6900 3350 60 0000 C CNN +F 3 "" H 6900 3350 60 0000 C CNN + 1 6900 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U5 +U 1 1 685AC23D +P 6900 4000 +F 0 "U5" H 6900 4000 60 0000 C CNN +F 1 "d_nor" H 6950 4100 60 0000 C CNN +F 2 "" H 6900 4000 60 0000 C CNN +F 3 "" H 6900 4000 60 0000 C CNN + 1 6900 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 685AC29F +P 8450 3650 +F 0 "U6" H 8450 3650 60 0000 C CNN +F 1 "d_nor" H 8500 3750 60 0000 C CNN +F 2 "" H 8450 3650 60 0000 C CNN +F 3 "" H 8450 3650 60 0000 C CNN + 1 8450 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3050 6450 3050 +Wire Wire Line + 6450 3050 6450 3250 +Wire Wire Line + 5100 4400 6000 4400 +Wire Wire Line + 6000 4400 6000 3350 +Wire Wire Line + 6000 3350 6450 3350 +Wire Wire Line + 5100 3700 6450 3700 +Wire Wire Line + 6450 3700 6450 3900 +Wire Wire Line + 6000 4000 6450 4000 +Connection ~ 6000 4000 +Wire Wire Line + 7350 3300 7350 3550 +Wire Wire Line + 7350 3550 8000 3550 +Wire Wire Line + 7350 3950 7350 3650 +Wire Wire Line + 7350 3650 8000 3650 +$Comp +L PORT U1 +U 1 1 685AC4F6 +P 4000 3700 +F 0 "U1" H 4050 3800 30 0000 C CNN +F 1 "PORT" H 4000 3700 30 0000 C CNN +F 2 "" H 4000 3700 60 0000 C CNN +F 3 "" H 4000 3700 60 0000 C CNN + 1 4000 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 685AC57C +P 4000 3050 +F 0 "U1" H 4050 3150 30 0000 C CNN +F 1 "PORT" H 4000 3050 30 0000 C CNN +F 2 "" H 4000 3050 60 0000 C CNN +F 3 "" H 4000 3050 60 0000 C CNN + 3 4000 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685AC5C3 +P 9500 3600 +F 0 "U1" H 9550 3700 30 0000 C CNN +F 1 "PORT" H 9500 3600 30 0000 C CNN +F 2 "" H 9500 3600 60 0000 C CNN +F 3 "" H 9500 3600 60 0000 C CNN + 4 9500 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 685AC803 +P 4100 4400 +F 0 "U1" H 4150 4500 30 0000 C CNN +F 1 "PORT" H 4100 4400 30 0000 C CNN +F 2 "" H 4100 4400 60 0000 C CNN +F 3 "" H 4100 4400 60 0000 C CNN + 6 4100 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4250 3050 4500 3050 +Wire Wire Line + 4250 3700 4500 3700 +Wire Wire Line + 4350 4400 4500 4400 +Wire Wire Line + 8900 3600 9250 3600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sub b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sub new file mode 100644 index 000000000..664a5de6c --- /dev/null +++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sub @@ -0,0 +1,30 @@ +* Subcircuit SN74AUP1G58 +.subckt SN74AUP1G58 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ +* c:\fossee\esim\library\subcircuitlibrary\sn74aup1g58\sn74aup1g58.cir +* u7 net-_u1-pad3_ net-_u4-pad1_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad6_ net-_u3-pad2_ d_inverter +* u4 net-_u4-pad1_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 net-_u2-pad2_ net-_u3-pad2_ net-_u5-pad3_ d_nor +* u6 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad4_ d_nor +a1 net-_u1-pad3_ net-_u4-pad1_ u7 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad6_ net-_u3-pad2_ u3 +a4 [net-_u4-pad1_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a5 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad4_ u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74AUP1G58 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58_Previous_Values.xml b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58_Previous_Values.xml new file mode 100644 index 000000000..a0ba30aa8 --- /dev/null +++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecd_inverterd_inverterd_inverterd_andd_nord_nor \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74AUP1G58/analysis b/library/SubcircuitLibrary/SN74AUP1G58/analysis new file mode 100644 index 000000000..0a6c83b5a --- /dev/null +++ b/library/SubcircuitLibrary/SN74AUP1G58/analysis @@ -0,0 +1 @@ +.tran 250e-03 10e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/cd4070b_ic/NMOS-180nm.lib b/library/SubcircuitLibrary/cd4070b_ic/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/cd4070b_ic/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/cd4070b_ic/PMOS-180nm.lib b/library/SubcircuitLibrary/cd4070b_ic/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/cd4070b_ic/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/cd4070b_ic/analysis b/library/SubcircuitLibrary/cd4070b_ic/analysis new file mode 100644 index 000000000..0a6c83b5a --- /dev/null +++ b/library/SubcircuitLibrary/cd4070b_ic/analysis @@ -0,0 +1 @@ +.tran 250e-03 10e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic-cache.lib b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic-cache.lib new file mode 100644 index 000000000..6c512720e --- /dev/null +++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir new file mode 100644 index 000000000..e9054ad73 --- /dev/null +++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir @@ -0,0 +1,22 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\cd4070b_ic\cd4070b_ic.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/23/25 22:05:51 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M3 Net-_M11-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M4 Net-_M11-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M6 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M10-Pad2_ Net-_M11-Pad1_ eSim_MOS_P +M5 Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ eSim_MOS_N +M8 Net-_M11-Pad1_ Net-_M2-Pad1_ Net-_M8-Pad3_ Net-_M11-Pad1_ eSim_MOS_P +M9 Net-_M8-Pad3_ Net-_M1-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad1_ eSim_MOS_P +M7 Net-_M10-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M1-Pad3_ eSim_MOS_N +M11 Net-_M11-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad2_ Net-_M11-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir.out b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir.out new file mode 100644 index 000000000..d2d1ea10b --- /dev/null +++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir.out @@ -0,0 +1,25 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4070b_ic\cd4070b_ic.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m11-pad1_ net-_m2-pad2_ net-_m2-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m11-pad1_ net-_m2-pad1_ net-_m8-pad3_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m9 net-_m8-pad3_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m7 net-_m10-pad2_ net-_m1-pad1_ net-_m2-pad1_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m11-pad1_ port +.tran 250e-03 10e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.pro b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sch b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sch new file mode 100644 index 000000000..73a3e929e --- /dev/null +++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sch @@ -0,0 +1,576 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_N M1 +U 1 1 68597EF6 +P 3200 2650 +F 0 "M1" H 3200 2500 50 0000 R CNN +F 1 "eSim_MOS_N" H 3300 2600 50 0000 R CNN +F 2 "" H 3500 2350 29 0000 C CNN +F 3 "" H 3300 2450 60 0000 C CNN + 1 3200 2650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M3 +U 1 1 68597EF7 +P 3250 2250 +F 0 "M3" H 3200 2300 50 0000 R CNN +F 1 "eSim_MOS_P" H 3300 2400 50 0000 R CNN +F 2 "" H 3500 2350 29 0000 C CNN +F 3 "" H 3300 2250 60 0000 C CNN + 1 3250 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 68597EF8 +P 3200 4200 +F 0 "M2" H 3200 4050 50 0000 R CNN +F 1 "eSim_MOS_N" H 3300 4150 50 0000 R CNN +F 2 "" H 3500 3900 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3200 4200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 68597EF9 +P 3250 3800 +F 0 "M4" H 3200 3850 50 0000 R CNN +F 1 "eSim_MOS_P" H 3300 3950 50 0000 R CNN +F 2 "" H 3500 3900 29 0000 C CNN +F 3 "" H 3300 3800 60 0000 C CNN + 1 3250 3800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 68597EFA +P 5600 3050 +F 0 "M6" H 5550 3100 50 0000 R CNN +F 1 "eSim_MOS_P" H 5650 3200 50 0000 R CNN +F 2 "" H 5850 3150 29 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5600 3050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M5 +U 1 1 68597EFB +P 4650 2850 +F 0 "M5" H 4650 2700 50 0000 R CNN +F 1 "eSim_MOS_N" H 4750 2800 50 0000 R CNN +F 2 "" H 4950 2550 29 0000 C CNN +F 3 "" H 4750 2650 60 0000 C CNN + 1 4650 2850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 68597EFC +P 6700 2350 +F 0 "M8" H 6650 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 6750 2500 50 0000 R CNN +F 2 "" H 6950 2450 29 0000 C CNN +F 3 "" H 6750 2350 60 0000 C CNN + 1 6700 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M9 +U 1 1 68597EFD +P 6700 3500 +F 0 "M9" H 6650 3550 50 0000 R CNN +F 1 "eSim_MOS_P" H 6750 3650 50 0000 R CNN +F 2 "" H 6950 3600 29 0000 C CNN +F 3 "" H 6750 3500 60 0000 C CNN + 1 6700 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 68597EFE +P 6650 3900 +F 0 "M7" H 6650 3750 50 0000 R CNN +F 1 "eSim_MOS_N" H 6750 3850 50 0000 R CNN +F 2 "" H 6950 3600 29 0000 C CNN +F 3 "" H 6750 3700 60 0000 C CNN + 1 6650 3900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 68597EFF +P 8150 2850 +F 0 "M11" H 8100 2900 50 0000 R CNN +F 1 "eSim_MOS_P" H 8200 3000 50 0000 R CNN +F 2 "" H 8400 2950 29 0000 C CNN +F 3 "" H 8200 2850 60 0000 C CNN + 1 8150 2850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 68597F00 +P 8050 3350 +F 0 "M10" H 8050 3200 50 0000 R CNN +F 1 "eSim_MOS_N" H 8150 3300 50 0000 R CNN +F 2 "" H 8350 3050 29 0000 C CNN +F 3 "" H 8150 3150 60 0000 C CNN + 1 8050 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 1550 3400 2050 +Wire Wire Line + 3400 1850 3650 1850 +Wire Wire Line + 3650 1850 3650 2450 +Wire Wire Line + 3650 2450 3500 2450 +Wire Wire Line + 3500 2450 3500 2400 +Wire Wire Line + 3400 2450 3400 2650 +Wire Wire Line + 3400 3050 3400 3200 +Wire Wire Line + 2450 3200 3500 3200 +Wire Wire Line + 3500 3200 3500 3000 +Wire Wire Line + 3100 2250 2750 2250 +Wire Wire Line + 2750 2250 2750 2850 +Wire Wire Line + 2750 2850 3100 2850 +Wire Wire Line + 3500 3950 3500 4000 +Wire Wire Line + 3500 4000 3600 4000 +Wire Wire Line + 3600 4000 3600 3500 +Wire Wire Line + 3600 3500 2350 3500 +Wire Wire Line + 3400 3500 3400 3600 +Wire Wire Line + 3400 4000 3400 4200 +Wire Wire Line + 3400 4600 3400 4700 +Wire Wire Line + 3500 4700 3500 4550 +Wire Wire Line + 3100 3800 2800 3800 +Wire Wire Line + 2800 3800 2800 4400 +Wire Wire Line + 2800 4400 3100 4400 +Wire Wire Line + 2350 3500 2350 1550 +Connection ~ 3400 3500 +Connection ~ 3400 1850 +Wire Wire Line + 4850 3250 4850 3400 +Wire Wire Line + 4850 3400 5450 3400 +Wire Wire Line + 5450 3400 5450 3250 +Wire Wire Line + 2450 4700 2450 3200 +Connection ~ 3400 4700 +Connection ~ 3400 3200 +Wire Wire Line + 4550 3050 4550 4100 +Wire Wire Line + 3400 4100 5450 4100 +Connection ~ 3400 4100 +Wire Wire Line + 4950 4700 4950 3200 +Connection ~ 3500 4700 +Wire Wire Line + 4850 2850 4850 2600 +Wire Wire Line + 4850 2600 5450 2600 +Wire Wire Line + 5450 2600 5450 2850 +Wire Wire Line + 3400 2550 6000 2550 +Wire Wire Line + 5200 2550 5200 2600 +Connection ~ 5200 2600 +Connection ~ 3400 2550 +Wire Wire Line + 5250 3200 5350 3200 +Wire Wire Line + 5250 1550 5250 3200 +Connection ~ 3400 1550 +Wire Wire Line + 2050 4100 2800 4100 +Wire Wire Line + 2600 4100 2600 3450 +Wire Wire Line + 2600 3450 5900 3450 +Wire Wire Line + 5900 3450 5900 3050 +Wire Wire Line + 5900 3050 5750 3050 +Connection ~ 2800 4100 +Wire Wire Line + 6550 3500 6200 3500 +Wire Wire Line + 6200 3500 6200 4100 +Wire Wire Line + 6200 4100 6550 4100 +Wire Wire Line + 6000 2550 6000 3750 +Wire Wire Line + 6000 3750 6200 3750 +Connection ~ 6200 3750 +Connection ~ 5200 2550 +Wire Wire Line + 6550 2350 6050 2350 +Wire Wire Line + 6050 2350 6050 4450 +Wire Wire Line + 5450 4450 6850 4450 +Wire Wire Line + 6850 4450 6850 4300 +Wire Wire Line + 5450 4100 5450 4450 +Connection ~ 4550 4100 +Connection ~ 6050 4450 +Wire Wire Line + 6950 4700 6950 4250 +Connection ~ 4950 4700 +Wire Wire Line + 6850 3700 6850 3900 +Wire Wire Line + 6850 2550 6850 3300 +Wire Wire Line + 6850 2150 6850 1950 +Wire Wire Line + 6850 1950 7250 1950 +Wire Wire Line + 7250 1550 7250 3650 +Wire Wire Line + 7250 2550 6950 2550 +Wire Wire Line + 6950 2550 6950 2500 +Wire Wire Line + 7250 3650 6950 3650 +Connection ~ 7250 2550 +Connection ~ 7250 1950 +Connection ~ 5250 1550 +Wire Wire Line + 8300 1550 8300 2650 +Connection ~ 7250 1550 +Wire Wire Line + 7700 2850 8000 2850 +Wire Wire Line + 7700 2850 7700 3550 +Wire Wire Line + 7700 3550 7950 3550 +Wire Wire Line + 8300 3050 8300 3250 +Wire Wire Line + 8250 3250 9700 3250 +Wire Wire Line + 8250 3250 8250 3350 +Wire Wire Line + 8250 3750 8250 4700 +Wire Wire Line + 8250 3900 8350 3900 +Wire Wire Line + 8350 3900 8350 3700 +Connection ~ 6950 4700 +Connection ~ 8250 3900 +Wire Wire Line + 6850 3800 7550 3800 +Wire Wire Line + 7550 3100 7550 4500 +Wire Wire Line + 7550 3100 7700 3100 +Connection ~ 7700 3100 +Connection ~ 6850 3800 +Wire Wire Line + 8300 2400 8550 2400 +Wire Wire Line + 8550 2400 8550 3000 +Wire Wire Line + 8550 3000 8400 3000 +Connection ~ 8300 2400 +Wire Wire Line + 7550 4500 5100 4500 +Wire Wire Line + 5100 4500 5100 3400 +Connection ~ 5100 3400 +Connection ~ 7550 3800 +Connection ~ 2750 2350 +Wire Wire Line + 2050 2650 2050 4100 +Connection ~ 2600 4100 +Connection ~ 8300 3250 +Connection ~ 8300 1550 +Wire Wire Line + 2350 1550 8300 1550 +Wire Wire Line + 2450 4700 10200 4700 +Connection ~ 8250 4700 +$Comp +L PORT U1 +U 1 1 68598A23 +P 850 3200 +F 0 "U1" H 900 3300 30 0000 C CNN +F 1 "PORT" H 850 3200 30 0000 C CNN +F 2 "" H 850 3200 60 0000 C CNN +F 3 "" H 850 3200 60 0000 C CNN + 1 850 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68598ACE +P 750 1600 +F 0 "U1" H 800 1700 30 0000 C CNN +F 1 "PORT" H 750 1600 30 0000 C CNN +F 2 "" H 750 1600 60 0000 C CNN +F 3 "" H 750 1600 60 0000 C CNN + 2 750 1600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68598B80 +P 9950 3250 +F 0 "U1" H 10000 3350 30 0000 C CNN +F 1 "PORT" H 9950 3250 30 0000 C CNN +F 2 "" H 9950 3250 60 0000 C CNN +F 3 "" H 9950 3250 60 0000 C CNN + 3 9950 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 68598E3D +P 9950 2950 +F 0 "U1" H 10000 3050 30 0000 C CNN +F 1 "PORT" H 9950 2950 30 0000 C CNN +F 2 "" H 9950 2950 60 0000 C CNN +F 3 "" H 9950 2950 60 0000 C CNN + 4 9950 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 68598EF2 +P 750 1950 +F 0 "U1" H 800 2050 30 0000 C CNN +F 1 "PORT" H 750 1950 30 0000 C CNN +F 2 "" H 750 1950 60 0000 C CNN +F 3 "" H 750 1950 60 0000 C CNN + 5 750 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 685990E3 +P 850 2950 +F 0 "U1" H 900 3050 30 0000 C CNN +F 1 "PORT" H 850 2950 30 0000 C CNN +F 2 "" H 850 2950 60 0000 C CNN +F 3 "" H 850 2950 60 0000 C CNN + 6 850 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68599207 +P 850 3550 +F 0 "U1" H 900 3650 30 0000 C CNN +F 1 "PORT" H 850 3550 30 0000 C CNN +F 2 "" H 850 3550 60 0000 C CNN +F 3 "" H 850 3550 60 0000 C CNN + 8 850 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 685992D0 +P 750 1300 +F 0 "U1" H 800 1400 30 0000 C CNN +F 1 "PORT" H 750 1300 30 0000 C CNN +F 2 "" H 750 1300 60 0000 C CNN +F 3 "" H 750 1300 60 0000 C CNN + 9 750 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6859946D +P 9950 3550 +F 0 "U1" H 10000 3650 30 0000 C CNN +F 1 "PORT" H 9950 3550 30 0000 C CNN +F 2 "" H 9950 3550 60 0000 C CNN +F 3 "" H 9950 3550 60 0000 C CNN + 10 9950 3550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6859964A +P 9950 3800 +F 0 "U1" H 10000 3900 30 0000 C CNN +F 1 "PORT" H 9950 3800 30 0000 C CNN +F 2 "" H 9950 3800 60 0000 C CNN +F 3 "" H 9950 3800 60 0000 C CNN + 11 9950 3800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 685997A5 +P 750 2200 +F 0 "U1" H 800 2300 30 0000 C CNN +F 1 "PORT" H 750 2200 30 0000 C CNN +F 2 "" H 750 2200 60 0000 C CNN +F 3 "" H 750 2200 60 0000 C CNN + 12 750 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6859980E +P 850 2650 +F 0 "U1" H 900 2750 30 0000 C CNN +F 1 "PORT" H 850 2650 30 0000 C CNN +F 2 "" H 850 2650 60 0000 C CNN +F 3 "" H 850 2650 60 0000 C CNN + 13 850 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 68599873 +P 5000 1150 +F 0 "U1" H 5050 1250 30 0000 C CNN +F 1 "PORT" H 5000 1150 30 0000 C CNN +F 2 "" H 5000 1150 60 0000 C CNN +F 3 "" H 5000 1150 60 0000 C CNN + 14 5000 1150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 1400 5000 1550 +Connection ~ 5000 1550 +Wire Wire Line + 2750 2350 1000 2350 +Wire Wire Line + 1000 2350 1000 2200 +Wire Wire Line + 1000 1300 1650 1300 +Wire Wire Line + 1650 1300 1650 2350 +Connection ~ 1650 2350 +Wire Wire Line + 1000 1600 1550 1600 +Wire Wire Line + 1550 1600 1550 2350 +Connection ~ 1550 2350 +Wire Wire Line + 1000 1950 1350 1950 +Wire Wire Line + 1350 1950 1350 2350 +Connection ~ 1350 2350 +Wire Wire Line + 1100 3550 2050 3550 +Connection ~ 2050 3550 +Wire Wire Line + 1100 3200 2050 3200 +Wire Wire Line + 1100 2950 2050 2950 +Connection ~ 2050 3200 +Wire Wire Line + 1100 2650 2050 2650 +Connection ~ 2050 2950 +Wire Wire Line + 9700 2950 9600 2950 +Wire Wire Line + 9600 2950 9600 3250 +Connection ~ 9600 3250 +Wire Wire Line + 9700 3550 9450 3550 +Wire Wire Line + 9450 3550 9450 3250 +Connection ~ 9450 3250 +Wire Wire Line + 9700 3800 9300 3800 +Wire Wire Line + 9300 3800 9300 3250 +Connection ~ 9300 3250 +$Comp +L PORT U1 +U 7 1 6859A8A9 +P 10450 4700 +F 0 "U1" H 10500 4800 30 0000 C CNN +F 1 "PORT" H 10450 4700 30 0000 C CNN +F 2 "" H 10450 4700 60 0000 C CNN +F 3 "" H 10450 4700 60 0000 C CNN + 7 10450 4700 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sub b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sub new file mode 100644 index 000000000..cbfbe6eae --- /dev/null +++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sub @@ -0,0 +1,19 @@ +* Subcircuit cd4070b_ic +.subckt cd4070b_ic net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m11-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\cd4070b_ic\cd4070b_ic.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m11-pad1_ net-_m2-pad2_ net-_m2-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m11-pad1_ net-_m2-pad1_ net-_m8-pad3_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m9 net-_m8-pad3_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m7 net-_m10-pad2_ net-_m1-pad1_ net-_m2-pad1_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends cd4070b_ic \ No newline at end of file diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic_Previous_Values.xml b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic_Previous_Values.xml new file mode 100644 index 000000000..025477594 --- /dev/null +++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/cd4077b/NMOS-180nm.lib b/library/SubcircuitLibrary/cd4077b/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/cd4077b/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/cd4077b/PMOS-180nm.lib b/library/SubcircuitLibrary/cd4077b/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/cd4077b/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/cd4077b/analysis b/library/SubcircuitLibrary/cd4077b/analysis new file mode 100644 index 000000000..0a6c83b5a --- /dev/null +++ b/library/SubcircuitLibrary/cd4077b/analysis @@ -0,0 +1 @@ +.tran 250e-03 10e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b-cache.lib b/library/SubcircuitLibrary/cd4077b/cd4077b-cache.lib new file mode 100644 index 000000000..6c512720e --- /dev/null +++ b/library/SubcircuitLibrary/cd4077b/cd4077b-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b.cir b/library/SubcircuitLibrary/cd4077b/cd4077b.cir new file mode 100644 index 000000000..7be5bf486 --- /dev/null +++ b/library/SubcircuitLibrary/cd4077b/cd4077b.cir @@ -0,0 +1,22 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\cd4077b\cd4077b.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 14:56:23 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M3 Net-_M11-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M4 Net-_M11-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M6 Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad1_ eSim_MOS_P +M5 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M10-Pad2_ Net-_M1-Pad3_ eSim_MOS_N +M7 Net-_M10-Pad2_ Net-_M1-Pad1_ Net-_M7-Pad3_ Net-_M7-Pad3_ eSim_MOS_N +M9 Net-_M2-Pad1_ Net-_M1-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad1_ eSim_MOS_P +M8 Net-_M7-Pad3_ Net-_M2-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M11 Net-_M11-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +U1 Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad2_ Net-_M11-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b.cir.out b/library/SubcircuitLibrary/cd4077b/cd4077b.cir.out new file mode 100644 index 000000000..fc6467d62 --- /dev/null +++ b/library/SubcircuitLibrary/cd4077b/cd4077b.cir.out @@ -0,0 +1,25 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4077b\cd4077b.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m11-pad1_ net-_m2-pad2_ net-_m2-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m10-pad2_ net-_m1-pad1_ net-_m7-pad3_ net-_m7-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m2-pad1_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m8 net-_m7-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +* u1 net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m11-pad1_ port +.tran 250e-03 10e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b.pro b/library/SubcircuitLibrary/cd4077b/cd4077b.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/cd4077b/cd4077b.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b.sch b/library/SubcircuitLibrary/cd4077b/cd4077b.sch new file mode 100644 index 000000000..6cbc04bf3 --- /dev/null +++ b/library/SubcircuitLibrary/cd4077b/cd4077b.sch @@ -0,0 +1,555 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_N M1 +U 1 1 685A6E8E +P 3050 2900 +F 0 "M1" H 3050 2750 50 0000 R CNN +F 1 "eSim_MOS_N" H 3150 2850 50 0000 R CNN +F 2 "" H 3350 2600 29 0000 C CNN +F 3 "" H 3150 2700 60 0000 C CNN + 1 3050 2900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M3 +U 1 1 685A6E8F +P 3100 2400 +F 0 "M3" H 3050 2450 50 0000 R CNN +F 1 "eSim_MOS_P" H 3150 2550 50 0000 R CNN +F 2 "" H 3350 2500 29 0000 C CNN +F 3 "" H 3150 2400 60 0000 C CNN + 1 3100 2400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 685A6E90 +P 3050 4350 +F 0 "M2" H 3050 4200 50 0000 R CNN +F 1 "eSim_MOS_N" H 3150 4300 50 0000 R CNN +F 2 "" H 3350 4050 29 0000 C CNN +F 3 "" H 3150 4150 60 0000 C CNN + 1 3050 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 685A6E91 +P 3100 3850 +F 0 "M4" H 3050 3900 50 0000 R CNN +F 1 "eSim_MOS_P" H 3150 4000 50 0000 R CNN +F 2 "" H 3350 3950 29 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 1 3100 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 685A6E92 +P 5500 3250 +F 0 "M6" H 5450 3300 50 0000 R CNN +F 1 "eSim_MOS_P" H 5550 3400 50 0000 R CNN +F 2 "" H 5750 3350 29 0000 C CNN +F 3 "" H 5550 3250 60 0000 C CNN + 1 5500 3250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M5 +U 1 1 685A6E93 +P 4650 3050 +F 0 "M5" H 4650 2900 50 0000 R CNN +F 1 "eSim_MOS_N" H 4750 3000 50 0000 R CNN +F 2 "" H 4950 2750 29 0000 C CNN +F 3 "" H 4750 2850 60 0000 C CNN + 1 4650 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 685A6E94 +P 6750 2750 +F 0 "M7" H 6750 2600 50 0000 R CNN +F 1 "eSim_MOS_N" H 6850 2700 50 0000 R CNN +F 2 "" H 7050 2450 29 0000 C CNN +F 3 "" H 6850 2550 60 0000 C CNN + 1 6750 2750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M9 +U 1 1 685A6E95 +P 6800 2350 +F 0 "M9" H 6750 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 6850 2500 50 0000 R CNN +F 2 "" H 7050 2450 29 0000 C CNN +F 3 "" H 6850 2350 60 0000 C CNN + 1 6800 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M8 +U 1 1 685A6E96 +P 6750 3700 +F 0 "M8" H 6750 3550 50 0000 R CNN +F 1 "eSim_MOS_N" H 6850 3650 50 0000 R CNN +F 2 "" H 7050 3400 29 0000 C CNN +F 3 "" H 6850 3500 60 0000 C CNN + 1 6750 3700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 685A6E97 +P 8150 3150 +F 0 "M10" H 8150 3000 50 0000 R CNN +F 1 "eSim_MOS_N" H 8250 3100 50 0000 R CNN +F 2 "" H 8450 2850 29 0000 C CNN +F 3 "" H 8250 2950 60 0000 C CNN + 1 8150 3150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 685A6E98 +P 8200 2600 +F 0 "M11" H 8150 2650 50 0000 R CNN +F 1 "eSim_MOS_P" H 8250 2750 50 0000 R CNN +F 2 "" H 8450 2700 29 0000 C CNN +F 3 "" H 8250 2600 60 0000 C CNN + 1 8200 2600 + 1 0 0 -1 +$EndComp +Connection ~ 5050 2750 +Connection ~ 6350 2750 +Wire Wire Line + 6350 2950 6650 2950 +Wire Wire Line + 6350 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7050 2500 7250 2500 +Wire Wire Line + 7250 2500 7250 2100 +Connection ~ 7250 2100 +Wire Wire Line + 5100 3650 5100 4500 +Wire Wire Line + 5100 4500 7400 4500 +Wire Wire Line + 7400 4500 7400 2650 +Wire Wire Line + 7400 2650 6950 2650 +Connection ~ 6950 2650 +Connection ~ 5100 3650 +Wire Wire Line + 7400 3000 7700 3000 +Connection ~ 7700 3000 +Connection ~ 7400 3000 +Connection ~ 2600 2750 +Connection ~ 2350 4200 +Connection ~ 8600 2100 +Wire Wire Line + 5650 5150 5650 4850 +Connection ~ 5650 4850 +Wire Wire Line + 1300 2750 2600 2750 +Wire Wire Line + 8350 2950 9450 2950 +Connection ~ 8350 2950 +Wire Wire Line + 2300 2100 10200 2100 +$Comp +L PORT U1 +U 1 1 685A74DB +P 1400 4200 +F 0 "U1" H 1450 4300 30 0000 C CNN +F 1 "PORT" H 1400 4200 30 0000 C CNN +F 2 "" H 1400 4200 60 0000 C CNN +F 3 "" H 1400 4200 60 0000 C CNN + 1 1400 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685A754E +P 1050 2750 +F 0 "U1" H 1100 2850 30 0000 C CNN +F 1 "PORT" H 1050 2750 30 0000 C CNN +F 2 "" H 1050 2750 60 0000 C CNN +F 3 "" H 1050 2750 60 0000 C CNN + 2 1050 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 685A767B +P 9700 2950 +F 0 "U1" H 9750 3050 30 0000 C CNN +F 1 "PORT" H 9700 2950 30 0000 C CNN +F 2 "" H 9700 2950 60 0000 C CNN +F 3 "" H 9700 2950 60 0000 C CNN + 3 9700 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 685A7834 +P 9700 3200 +F 0 "U1" H 9750 3300 30 0000 C CNN +F 1 "PORT" H 9700 3200 30 0000 C CNN +F 2 "" H 9700 3200 60 0000 C CNN +F 3 "" H 9700 3200 60 0000 C CNN + 4 9700 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 685A7930 +P 1050 2400 +F 0 "U1" H 1100 2500 30 0000 C CNN +F 1 "PORT" H 1050 2400 30 0000 C CNN +F 2 "" H 1050 2400 60 0000 C CNN +F 3 "" H 1050 2400 60 0000 C CNN + 5 1050 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 685A796D +P 1400 3900 +F 0 "U1" H 1450 4000 30 0000 C CNN +F 1 "PORT" H 1400 3900 30 0000 C CNN +F 2 "" H 1400 3900 60 0000 C CNN +F 3 "" H 1400 3900 60 0000 C CNN + 6 1400 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 685A7A53 +P 5650 5400 +F 0 "U1" H 5700 5500 30 0000 C CNN +F 1 "PORT" H 5650 5400 30 0000 C CNN +F 2 "" H 5650 5400 60 0000 C CNN +F 3 "" H 5650 5400 60 0000 C CNN + 7 5650 5400 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 685A7C28 +P 1400 4500 +F 0 "U1" H 1450 4600 30 0000 C CNN +F 1 "PORT" H 1400 4500 30 0000 C CNN +F 2 "" H 1400 4500 60 0000 C CNN +F 3 "" H 1400 4500 60 0000 C CNN + 8 1400 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 685A7DF4 +P 1050 2950 +F 0 "U1" H 1100 3050 30 0000 C CNN +F 1 "PORT" H 1050 2950 30 0000 C CNN +F 2 "" H 1050 2950 60 0000 C CNN +F 3 "" H 1050 2950 60 0000 C CNN + 9 1050 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685A7E75 +P 9700 3450 +F 0 "U1" H 9750 3550 30 0000 C CNN +F 1 "PORT" H 9700 3450 30 0000 C CNN +F 2 "" H 9700 3450 60 0000 C CNN +F 3 "" H 9700 3450 60 0000 C CNN + 10 9700 3450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 685A80FC +P 9700 3650 +F 0 "U1" H 9750 3750 30 0000 C CNN +F 1 "PORT" H 9700 3650 30 0000 C CNN +F 2 "" H 9700 3650 60 0000 C CNN +F 3 "" H 9700 3650 60 0000 C CNN + 11 9700 3650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 685A814D +P 1050 2150 +F 0 "U1" H 1100 2250 30 0000 C CNN +F 1 "PORT" H 1050 2150 30 0000 C CNN +F 2 "" H 1050 2150 60 0000 C CNN +F 3 "" H 1050 2150 60 0000 C CNN + 12 1050 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 685A83A6 +P 1400 3650 +F 0 "U1" H 1450 3750 30 0000 C CNN +F 1 "PORT" H 1400 3650 30 0000 C CNN +F 2 "" H 1400 3650 60 0000 C CNN +F 3 "" H 1400 3650 60 0000 C CNN + 13 1400 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 685A84E7 +P 10450 2100 +F 0 "U1" H 10500 2200 30 0000 C CNN +F 1 "PORT" H 10450 2100 30 0000 C CNN +F 2 "" H 10450 2100 60 0000 C CNN +F 3 "" H 10450 2100 60 0000 C CNN + 14 10450 2100 + -1 0 0 1 +$EndComp +Wire Wire Line + 9450 3200 9350 3200 +Wire Wire Line + 9350 3200 9350 2950 +Connection ~ 9350 2950 +Wire Wire Line + 9450 3450 9200 3450 +Wire Wire Line + 9200 3450 9200 2950 +Connection ~ 9200 2950 +Wire Wire Line + 9450 3650 9050 3650 +Wire Wire Line + 9050 3650 9050 2950 +Connection ~ 9050 2950 +Wire Wire Line + 1300 2150 1500 2150 +Wire Wire Line + 1500 2150 1500 2950 +Wire Wire Line + 1300 2400 1500 2400 +Connection ~ 1500 2400 +Connection ~ 1500 2750 +Wire Wire Line + 1500 2950 1300 2950 +Wire Wire Line + 1650 3650 1900 3650 +Wire Wire Line + 1900 3650 1900 4500 +Wire Wire Line + 1650 3900 1900 3900 +Connection ~ 1900 3900 +Connection ~ 1900 4200 +Wire Wire Line + 1900 4500 1650 4500 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b.sub b/library/SubcircuitLibrary/cd4077b/cd4077b.sub new file mode 100644 index 000000000..183a479ea --- /dev/null +++ b/library/SubcircuitLibrary/cd4077b/cd4077b.sub @@ -0,0 +1,19 @@ +* Subcircuit cd4077b +.subckt cd4077b net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m11-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\cd4077b\cd4077b.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m11-pad1_ net-_m2-pad2_ net-_m2-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m10-pad2_ net-_m1-pad1_ net-_m7-pad3_ net-_m7-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m2-pad1_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m8 net-_m7-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +* Control Statements + +.ends cd4077b \ No newline at end of file diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b_Previous_Values.xml b/library/SubcircuitLibrary/cd4077b/cd4077b_Previous_Values.xml new file mode 100644 index 000000000..e8d19e0d7 --- /dev/null +++ b/library/SubcircuitLibrary/cd4077b/cd4077b_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssec \ No newline at end of file diff --git a/library/SubcircuitLibrary/dm74ls51/3_and-cache.lib b/library/SubcircuitLibrary/dm74ls51/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/dm74ls51/3_and.cir b/library/SubcircuitLibrary/dm74ls51/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/dm74ls51/3_and.cir.out b/library/SubcircuitLibrary/dm74ls51/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/dm74ls51/3_and.pro b/library/SubcircuitLibrary/dm74ls51/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/dm74ls51/3_and.sch b/library/SubcircuitLibrary/dm74ls51/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/dm74ls51/3_and.sub b/library/SubcircuitLibrary/dm74ls51/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/dm74ls51/3_and_Previous_Values.xml b/library/SubcircuitLibrary/dm74ls51/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/dm74ls51/analysis b/library/SubcircuitLibrary/dm74ls51/analysis new file mode 100644 index 000000000..0a6c83b5a --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/analysis @@ -0,0 +1 @@ +.tran 250e-03 10e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51-cache.lib b/library/SubcircuitLibrary/dm74ls51/dm74ls51-cache.lib new file mode 100644 index 000000000..cf18b4a95 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir b/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir new file mode 100644 index 000000000..e148710b4 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\dm74ls51\dm74ls51.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/03/25 20:46:55 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad1_ Net-_U3-Pad1_ 3_and +X2 Net-_U1-Pad11_ Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U3-Pad2_ 3_and +U5 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad1_ d_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U1-Pad8_ d_nor +U4 Net-_U4-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ PORT + +.end diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir.out b/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir.out new file mode 100644 index 000000000..8494a0915 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir.out @@ -0,0 +1,31 @@ +* c:\fossee\esim\library\subcircuitlibrary\dm74ls51\dm74ls51.cir + +.include 3_and.sub +x1 net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad1_ net-_u3-pad1_ 3_and +x2 net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u3-pad2_ 3_and +* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad1_ d_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u1-pad8_ d_nor +* u4 net-_u4-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad1_ u5 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a3 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u1-pad8_ u3 +a4 [net-_u4-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u4 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 250e-03 10e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51.pro b/library/SubcircuitLibrary/dm74ls51/dm74ls51.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51.sch b/library/SubcircuitLibrary/dm74ls51/dm74ls51.sch new file mode 100644 index 000000000..7f0d40034 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51.sch @@ -0,0 +1,312 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 68669C7A +P 5350 2450 +F 0 "X1" H 5450 2400 60 0000 C CNN +F 1 "3_and" H 5500 2600 60 0000 C CNN +F 2 "" H 5350 2450 60 0000 C CNN +F 3 "" H 5350 2450 60 0000 C CNN + 1 5350 2450 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 68669CC5 +P 5350 2950 +F 0 "X2" H 5450 2900 60 0000 C CNN +F 1 "3_and" H 5500 3100 60 0000 C CNN +F 2 "" H 5350 2950 60 0000 C CNN +F 3 "" H 5350 2950 60 0000 C CNN + 1 5350 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 68669D04 +P 5400 3900 +F 0 "U5" H 5400 3900 60 0000 C CNN +F 1 "d_and" H 5450 4000 60 0000 C CNN +F 2 "" H 5400 3900 60 0000 C CNN +F 3 "" H 5400 3900 60 0000 C CNN + 1 5400 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 68669D39 +P 5400 4300 +F 0 "U2" H 5400 4300 60 0000 C CNN +F 1 "d_and" H 5450 4400 60 0000 C CNN +F 2 "" H 5400 4300 60 0000 C CNN +F 3 "" H 5400 4300 60 0000 C CNN + 1 5400 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U3 +U 1 1 68669D6A +P 6650 2700 +F 0 "U3" H 6650 2700 60 0000 C CNN +F 1 "d_nor" H 6700 2800 60 0000 C CNN +F 2 "" H 6650 2700 60 0000 C CNN +F 3 "" H 6650 2700 60 0000 C CNN + 1 6650 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U4 +U 1 1 68669DBD +P 6750 4100 +F 0 "U4" H 6750 4100 60 0000 C CNN +F 1 "d_nor" H 6800 4200 60 0000 C CNN +F 2 "" H 6750 4100 60 0000 C CNN +F 3 "" H 6750 4100 60 0000 C CNN + 1 6750 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 68669E78 +P 3650 1950 +F 0 "U1" H 3700 2050 30 0000 C CNN +F 1 "PORT" H 3650 1950 30 0000 C CNN +F 2 "" H 3650 1950 60 0000 C CNN +F 3 "" H 3650 1950 60 0000 C CNN + 1 3650 1950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 68669F10 +P 4250 3450 +F 0 "U1" H 4300 3550 30 0000 C CNN +F 1 "PORT" H 4250 3450 30 0000 C CNN +F 2 "" H 4250 3450 60 0000 C CNN +F 3 "" H 4250 3450 60 0000 C CNN + 2 4250 3450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 68669FB7 +P 4000 3450 +F 0 "U1" H 4050 3550 30 0000 C CNN +F 1 "PORT" H 4000 3450 30 0000 C CNN +F 2 "" H 4000 3450 60 0000 C CNN +F 3 "" H 4000 3450 60 0000 C CNN + 3 4000 3450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 68669FF6 +P 4000 4700 +F 0 "U1" H 4050 4800 30 0000 C CNN +F 1 "PORT" H 4000 4700 30 0000 C CNN +F 2 "" H 4000 4700 60 0000 C CNN +F 3 "" H 4000 4700 60 0000 C CNN + 4 4000 4700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 6866A06F +P 4250 4700 +F 0 "U1" H 4300 4800 30 0000 C CNN +F 1 "PORT" H 4250 4700 30 0000 C CNN +F 2 "" H 4250 4700 60 0000 C CNN +F 3 "" H 4250 4700 60 0000 C CNN + 5 4250 4700 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 2400 6200 2400 +Wire Wire Line + 6200 2400 6200 2600 +Wire Wire Line + 6200 2700 6200 2900 +Wire Wire Line + 6200 2900 5850 2900 +Wire Wire Line + 5850 3850 6300 3850 +Wire Wire Line + 6300 3850 6300 4000 +Wire Wire Line + 6300 4100 6300 4250 +Wire Wire Line + 6300 4250 5850 4250 +Wire Wire Line + 4250 3700 4250 3800 +Wire Wire Line + 4250 3800 4950 3800 +Wire Wire Line + 4950 3900 4000 3900 +Wire Wire Line + 4000 3900 4000 3700 +Wire Wire Line + 4250 4450 4250 4300 +Wire Wire Line + 4250 4300 4950 4300 +Wire Wire Line + 4950 4200 4000 4200 +Wire Wire Line + 4000 4200 4000 4450 +$Comp +L PORT U1 +U 6 1 6866A23A +P 7800 4050 +F 0 "U1" H 7850 4150 30 0000 C CNN +F 1 "PORT" H 7800 4050 30 0000 C CNN +F 2 "" H 7800 4050 60 0000 C CNN +F 3 "" H 7800 4050 60 0000 C CNN + 6 7800 4050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 6866A31C +P 7700 2650 +F 0 "U1" H 7750 2750 30 0000 C CNN +F 1 "PORT" H 7700 2650 30 0000 C CNN +F 2 "" H 7700 2650 60 0000 C CNN +F 3 "" H 7700 2650 60 0000 C CNN + 8 7700 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 6866A3A3 +P 3450 3100 +F 0 "U1" H 3500 3200 30 0000 C CNN +F 1 "PORT" H 3450 3100 30 0000 C CNN +F 2 "" H 3450 3100 60 0000 C CNN +F 3 "" H 3450 3100 60 0000 C CNN + 9 3450 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6866A498 +P 3450 2900 +F 0 "U1" H 3500 3000 30 0000 C CNN +F 1 "PORT" H 3450 2900 30 0000 C CNN +F 2 "" H 3450 2900 60 0000 C CNN +F 3 "" H 3450 2900 60 0000 C CNN + 10 3450 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6866A522 +P 3450 2700 +F 0 "U1" H 3500 2800 30 0000 C CNN +F 1 "PORT" H 3450 2700 30 0000 C CNN +F 2 "" H 3450 2700 60 0000 C CNN +F 3 "" H 3450 2700 60 0000 C CNN + 11 3450 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6866A569 +P 4250 1950 +F 0 "U1" H 4300 2050 30 0000 C CNN +F 1 "PORT" H 4250 1950 30 0000 C CNN +F 2 "" H 4250 1950 60 0000 C CNN +F 3 "" H 4250 1950 60 0000 C CNN + 12 4250 1950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 6866A5B8 +P 3950 1950 +F 0 "U1" H 4000 2050 30 0000 C CNN +F 1 "PORT" H 3950 1950 30 0000 C CNN +F 2 "" H 3950 1950 60 0000 C CNN +F 3 "" H 3950 1950 60 0000 C CNN + 13 3950 1950 + 0 1 1 0 +$EndComp +Wire Wire Line + 4250 2200 5000 2200 +Wire Wire Line + 5000 2200 5000 2300 +Wire Wire Line + 3950 2200 3950 2400 +Wire Wire Line + 3950 2400 5000 2400 +Wire Wire Line + 3650 2200 3650 2500 +Wire Wire Line + 3650 2500 5000 2500 +Wire Wire Line + 3700 2700 5000 2700 +Wire Wire Line + 5000 2700 5000 2800 +Wire Wire Line + 5000 2900 3700 2900 +Wire Wire Line + 3700 3100 5000 3100 +Wire Wire Line + 5000 3100 5000 3000 +Wire Wire Line + 7200 4050 7550 4050 +Wire Wire Line + 7100 2650 7450 2650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51.sub b/library/SubcircuitLibrary/dm74ls51/dm74ls51.sub new file mode 100644 index 000000000..35c5445f8 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51.sub @@ -0,0 +1,25 @@ +* Subcircuit dm74ls51 +.subckt dm74ls51 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ +* c:\fossee\esim\library\subcircuitlibrary\dm74ls51\dm74ls51.cir +.include 3_and.sub +x1 net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad1_ net-_u3-pad1_ 3_and +x2 net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u3-pad2_ 3_and +* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad1_ d_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u1-pad8_ d_nor +* u4 net-_u4-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_nor +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad1_ u5 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a3 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u1-pad8_ u3 +a4 [net-_u4-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u4 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends dm74ls51 \ No newline at end of file diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51_Previous_Values.xml b/library/SubcircuitLibrary/dm74ls51/dm74ls51_Previous_Values.xml new file mode 100644 index 000000000..1f9d5b233 --- /dev/null +++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecd_andd_andd_nord_norC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/eSim_Subckt.lib b/library/SubcircuitLibrary/eSim_Subckt.lib index 56cddf041..f95dfd269 100644 --- a/library/SubcircuitLibrary/eSim_Subckt.lib +++ b/library/SubcircuitLibrary/eSim_Subckt.lib @@ -148,186 +148,31 @@ X out 6 550 0 200 L 50 50 1 1 O ENDDRAW ENDDEF # -# 74HC194 +# 74hc151d # -DEF 74HC194 X 0 40 Y Y 1 F N -F0 "X" 50 300 60 H V C CNN -F1 "74HC194" 50 550 60 H V C CNN -F2 "" 50 300 60 H I C CNN -F3 "" 50 300 60 H I C CNN -DRAW -A 0 1350 100 -1799 -1 0 1 0 N -100 1350 100 1350 -S -400 1350 450 -750 0 1 0 N -X MR_bar 1 -600 1200 200 R 50 50 1 1 I -X DSR 2 -600 950 200 R 50 50 1 1 I -X D0 3 -600 700 200 R 50 50 1 1 I -X D1 4 -600 450 200 R 50 50 1 1 I -X D2 5 -600 200 200 R 50 50 1 1 I -X D3 6 -600 -50 200 R 50 50 1 1 I -X DSL 7 -600 -300 200 R 50 50 1 1 I -X GND 8 -600 -550 200 R 50 50 1 1 I -X S0 9 650 -550 200 L 50 50 1 1 I -X S1 10 650 -300 200 L 50 50 1 1 I -X CP 11 650 -50 200 L 50 50 1 1 I -X Q3 12 650 200 200 L 50 50 1 1 O -X Q2 13 650 450 200 L 50 50 1 1 O -X Q1 14 650 700 200 L 50 50 1 1 O -X Q0 15 650 950 200 L 50 50 1 1 O -X VCC 16 650 1200 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# AN1186 -# -DEF AN1186 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "AN1186" -50 400 60 H V C CNN -F2 "" -50 400 60 H I C CNN -F3 "" -50 400 60 H I C CNN -DRAW -S -350 350 250 -350 0 1 0 N -X Clk 1 -550 300 200 R 50 50 1 1 I -X rst 2 -550 200 200 R 50 50 1 1 I -X data_in 3 -550 100 200 R 50 50 1 1 I -X q0 4 -550 0 200 R 50 50 1 1 O -X q1 5 -550 -100 200 R 50 50 1 1 O -X q2 6 -550 -200 200 R 50 50 1 1 O -X Gnd 7 -550 -300 200 R 50 50 1 1 I -X q3 8 450 -300 200 L 50 50 1 1 O -X q4 9 450 -200 200 L 50 50 1 1 O -X q5 10 450 -100 200 L 50 50 1 1 O -X q6 11 450 0 200 L 50 50 1 1 O -X q7 12 450 100 200 L 50 50 1 1 O -X NC 13 450 200 200 L 50 50 1 1 I -X Vcc 14 450 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# AN1186_CRC -# -DEF AN1186_CRC U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "AN1186_CRC" -50 400 60 H V C CNN -F2 "" -50 400 60 H I C CNN -F3 "" -50 400 60 H I C CNN -DRAW -S -350 350 250 -350 0 1 0 N -X Clk 1 -550 300 200 R 50 50 1 1 I -X rst 2 -550 200 200 R 50 50 1 1 I -X data_in 3 -550 100 200 R 50 50 1 1 I -X q0 4 -550 0 200 R 50 50 1 1 O -X q1 5 -550 -100 200 R 50 50 1 1 O -X q2 6 -550 -200 200 R 50 50 1 1 O -X Gnd 7 -550 -300 200 R 50 50 1 1 I -X q3 8 450 -300 200 L 50 50 1 1 O -X q4 9 450 -200 200 L 50 50 1 1 O -X q5 10 450 -100 200 L 50 50 1 1 O -X q6 11 450 0 200 L 50 50 1 1 O -X q7 12 450 100 200 L 50 50 1 1 O -X NC 13 450 200 200 L 50 50 1 1 I -X Vcc 14 450 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# AN1186_CRC_Gen -# -DEF AN1186_CRC_Gen X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "AN1186_CRC_Gen" 0 400 60 H V C CNN -F2 "" 0 -100 60 H I C CNN -F3 "" 0 -100 60 H I C CNN -DRAW -S -300 350 250 -400 0 1 0 N -X Clk 1 -500 250 200 R 50 50 1 1 I -X Rst 2 -500 150 200 R 50 50 1 1 I -X Data_in 3 -500 50 200 R 50 50 1 1 I -X q0 4 -500 -50 200 R 50 50 1 1 O -X q1 5 -500 -150 200 R 50 50 1 1 O -X q2 6 -500 -250 200 R 50 50 1 1 O -X Gnd 7 -500 -350 200 R 50 50 1 1 I -X q3 8 450 -350 200 L 50 50 1 1 O -X q4 9 450 -250 200 L 50 50 1 1 O -X q5 10 450 -150 200 L 50 50 1 1 O -X q6 11 450 -50 200 L 50 50 1 1 O -X q7 12 450 50 200 L 50 50 1 1 O -X NC 13 450 150 200 L 50 50 1 1 I -X Vcc 14 450 250 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# Bidirectional_switch -# -DEF Bidirectional_switch X 0 40 Y Y 1 F N -F0 "X" -150 -200 60 H V C CNN -F1 "Bidirectional_switch" 50 0 60 H V C CNN -F2 "" 50 0 60 H I C CNN -F3 "" 50 0 60 H I C CNN -DRAW -P 2 0 1 0 150 -250 500 -250 N -P 3 0 1 0 -400 -250 -100 -250 150 -100 N -X ~ 1 -550 -250 200 R 50 50 1 1 B -X ~ 2 700 -250 200 L 50 50 1 1 B -X ~ 3 -100 -450 200 U 50 50 1 1 B -ENDDRAW -ENDDEF -# -# CBTL02043A -# -DEF CBTL02043A X 0 40 Y Y 1 F N -F0 "X" 1550 750 60 H V C CNN -F1 "CBTL02043A" 1550 850 60 H V C CNN -F2 "" 1550 850 60 H I C CNN -F3 "" 1550 850 60 H I C CNN -DRAW -S 1200 800 1850 -250 0 1 0 N -X Vdd 1 1000 700 200 R 50 50 1 1 I -X XSD 2 1000 600 200 R 50 50 1 1 I -X A0_P 3 1000 500 200 R 50 50 1 1 B -X A0_N 4 1000 400 200 R 50 50 1 1 B -X GND 5 1000 300 200 R 50 50 1 1 I -X Vdd 6 1000 200 200 R 50 50 1 1 I -X A1_P 7 1000 100 200 R 50 50 1 1 B -X A1_N 8 1000 0 200 R 50 50 1 1 B -X SEL 9 1000 -100 200 R 50 50 1 1 I -X VDD 10 1000 -200 200 R 50 50 1 1 I -X GND 20 2050 700 200 L 50 50 1 1 I -X GND 11 2050 -200 200 L 50 50 1 1 I -X C1_N 12 2050 -100 200 L 50 50 1 1 B -X C1_P 13 2050 0 200 L 50 50 1 1 B -X C0_N 14 2050 100 200 L 50 50 1 1 B -X C0_P 15 2050 200 200 L 50 50 1 1 B -X B1_N 16 2050 300 200 L 50 50 1 1 B -X B1_P 17 2050 400 200 L 50 50 1 1 B -X B0_N 18 2050 500 200 L 50 50 1 1 B -X B0_P 19 2050 600 200 L 50 50 1 1 B -ENDDRAW -ENDDEF -# -# CD4048BMS -# -DEF CD4048BMS X 0 40 Y Y 1 F N -F0 "X" 0 300 60 H V C CNN -F1 "CD4048BMS" -50 950 60 H V C CNN -F2 "" -50 950 60 H I C CNN -F3 "" -50 950 60 H I C CNN +DEF 74hc151d X 0 40 Y Y 1 F N +F0 "X" -100 -600 60 H V C CNN +F1 "74hc151d" -50 500 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN DRAW -S -450 900 400 -300 0 1 0 N -X J(O/P) 1 -650 800 200 R 50 50 1 1 O -X Kd 2 -650 650 200 R 50 50 1 1 I -X H 3 -650 500 200 R 50 50 1 1 I -X G 4 -650 350 200 R 50 50 1 1 I -X F 5 -650 200 200 R 50 50 1 1 I -X E 6 -650 50 200 R 50 50 1 1 I -X Kb 7 -650 -100 200 R 50 50 1 1 I -X VSS 8 -650 -250 200 R 50 50 1 1 I -X Kc 9 600 -250 200 L 50 50 1 1 I -X Ka 10 600 -100 200 L 50 50 1 1 I -X D 11 600 50 200 L 50 50 1 1 I -X C 12 600 200 200 L 50 50 1 1 I -X B 13 600 350 200 L 50 50 1 1 I -X A 14 600 500 200 L 50 50 1 1 I -X Expand 15 600 650 200 L 50 50 1 1 I -X VDD 16 600 800 200 L 50 50 1 1 I +S -350 450 200 -500 0 1 0 N +X i3 1 -550 350 200 R 50 50 1 1 I +X i2 2 -550 250 200 R 50 50 1 1 I +X i1 3 -550 150 200 R 50 50 1 1 I +X i0 4 -550 50 200 R 50 50 1 1 I +X y 5 -550 -50 200 R 50 50 1 1 O +X ybar 6 -550 -150 200 R 50 50 1 1 O +X en 7 -550 -250 200 R 50 50 1 1 I +X gnd 8 -550 -350 200 R 50 50 1 1 P +X s2 9 400 350 200 L 50 50 1 1 I +X s1 10 400 250 200 L 50 50 1 1 I +X s0 11 400 150 200 L 50 50 1 1 I +X i7 12 400 50 200 L 50 50 1 1 I +X i6 13 400 -50 200 L 50 50 1 1 I +X i5 14 400 -150 200 L 50 50 1 1 I +X i4 15 400 -250 200 L 50 50 1 1 I +X vcc 16 400 -350 200 L 50 50 1 1 W ENDDRAW ENDDEF # @@ -365,87 +210,6 @@ X Clkout 4 800 0 200 L 50 50 1 1 O ENDDRAW ENDDEF # -# DFF -# -DEF DFF X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "DFF" 0 100 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -550 750 550 -500 0 1 0 N -X D 1 -750 550 200 R 50 50 1 1 I -X CLK 2 -750 -250 200 R 50 50 1 1 I -X SET 3 0 950 200 D 50 50 1 1 I -X RESET 4 0 -700 200 U 50 50 1 1 I -X Q 5 750 550 200 L 50 50 1 1 O -X Q_bar 6 750 -250 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC-LM3900 -# -DEF IC-LM3900 X 0 40 Y Y 1 F N -F0 "X" 0 -300 60 H V C CNN -F1 "IC-LM3900" 0 -200 60 H V C CNN -F2 "" 0 -200 60 H I C CNN -F3 "" 0 -200 60 H I C CNN -DRAW -A -1200 -100 150 -899 899 0 0 0 N -1200 -250 -1200 50 -T 0 -550 -500 60 0 0 0 + Normal 0 C C -T 0 -550 50 60 0 0 0 + Normal 0 C C -T 0 750 -300 60 0 0 0 + Normal 0 C C -T 0 750 250 60 0 0 0 + Normal 0 C C -T 0 -550 -250 60 0 0 0 - Normal 0 C C -T 0 -550 300 60 0 0 0 - Normal 0 C C -T 0 750 -500 60 0 0 0 - Normal 0 C C -T 0 750 50 60 0 0 0 - Normal 0 C C -T 0 650 -400 60 0 0 0 1 Normal 0 C C -T 0 -450 -400 60 0 0 0 2 Normal 0 C C -T 0 650 150 60 0 0 0 3 Normal 0 C C -T 0 -450 150 60 0 0 0 4 Normal 0 C C -S -1200 750 1150 -1050 0 0 0 N -P 3 0 0 0 -600 -550 -650 -550 -650 -800 N -P 3 0 0 0 -200 -400 50 -400 50 -800 N -P 3 0 0 0 400 -400 350 -400 350 -800 N -P 3 0 0 0 800 0 950 0 950 500 N -P 5 0 0 0 -600 -250 -800 -250 -800 -700 -300 -700 -300 -800 N -P 5 0 0 0 -600 0 -800 0 -800 400 -300 400 -300 500 N -P 5 0 0 0 -600 300 -700 300 -700 450 50 450 50 500 N -P 5 0 0 0 -200 150 150 150 150 450 350 450 350 500 N -P 5 0 0 0 400 150 250 150 250 400 650 400 650 500 N -P 5 0 0 0 800 -550 900 -550 900 -750 650 -750 650 -800 N -P 5 0 0 0 800 -250 950 -250 950 -650 -950 -650 -950 -800 N -P 6 0 0 0 800 300 1000 300 1000 -100 -1000 -100 -1000 500 -650 500 N -C -600 -400 71 0 1 0 N -C -600 150 71 0 1 0 N -C 800 -400 71 0 1 0 N -C 800 150 71 0 1 0 N -P 4 0 1 0 -650 -350 -600 -450 -550 -350 -650 -350 N -P 4 0 1 0 -650 200 -600 100 -550 200 -650 200 N -P 4 0 1 0 -600 -200 -600 -600 -200 -400 -600 -200 N -P 4 0 1 0 -600 350 -600 -50 -200 150 -600 350 N -P 4 0 1 0 800 -600 800 -200 400 -400 800 -600 N -P 4 0 1 0 800 -50 800 350 400 150 800 -50 N -P 4 0 1 0 850 -450 800 -350 750 -450 850 -450 N -P 4 0 1 0 850 100 800 200 750 100 850 100 N -X IN1+ 1 -950 -1250 200 U 50 50 1 1 I -X IN2+ 2 -650 -1250 200 U 50 50 1 1 I -X IN2- 3 -300 -1250 200 U 50 50 1 1 I -X OUT2 4 50 -1250 200 U 50 50 1 1 O -X OUT1 5 350 -1250 200 U 50 50 1 1 O -X IN1- 6 650 -1250 200 U 50 50 1 1 I -X GND 7 950 -1250 200 U 50 50 1 1 I -X IN3- 8 950 950 200 D 50 50 1 1 I -X OUT3 9 650 950 200 D 50 50 1 1 O -X OUT4 10 350 950 200 D 50 50 1 1 O -X IN4- 11 50 950 200 D 50 50 1 1 I -X IN4+ 12 -300 950 200 D 50 50 1 1 I -X IN3+ 13 -650 950 200 D 50 50 1 1 I -X VCC 14 -950 950 200 D 50 50 1 1 I -ENDDRAW -ENDDEF -# # IC_4002 # DEF IC_4002 X 0 40 Y Y 1 F N @@ -725,25 +489,6 @@ X A plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/f100102/f100102.pro b/library/SubcircuitLibrary/f100102/f100102.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/f100102/f100102.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/f100102/f100102.sch b/library/SubcircuitLibrary/f100102/f100102.sch new file mode 100644 index 000000000..cce2457fe --- /dev/null +++ b/library/SubcircuitLibrary/f100102/f100102.sch @@ -0,0 +1,586 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 68680518 +P 4100 1800 +F 0 "U2" H 4100 1800 60 0000 C CNN +F 1 "d_or" H 4100 1900 60 0000 C CNN +F 2 "" H 4100 1800 60 0000 C CNN +F 3 "" H 4100 1800 60 0000 C CNN + 1 4100 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 68680541 +P 5150 2050 +F 0 "U6" H 5150 2050 60 0000 C CNN +F 1 "d_or" H 5150 2150 60 0000 C CNN +F 2 "" H 5150 2050 60 0000 C CNN +F 3 "" H 5150 2050 60 0000 C CNN + 1 5150 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 686805B7 +P 4100 2400 +F 0 "U3" H 4100 2400 60 0000 C CNN +F 1 "d_or" H 4100 2500 60 0000 C CNN +F 2 "" H 4100 2400 60 0000 C CNN +F 3 "" H 4100 2400 60 0000 C CNN + 1 4100 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U7 +U 1 1 686805BD +P 5150 2650 +F 0 "U7" H 5150 2650 60 0000 C CNN +F 1 "d_or" H 5150 2750 60 0000 C CNN +F 2 "" H 5150 2650 60 0000 C CNN +F 3 "" H 5150 2650 60 0000 C CNN + 1 5150 2650 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 6868075B +P 4100 3050 +F 0 "U4" H 4100 3050 60 0000 C CNN +F 1 "d_or" H 4100 3150 60 0000 C CNN +F 2 "" H 4100 3050 60 0000 C CNN +F 3 "" H 4100 3050 60 0000 C CNN + 1 4100 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U8 +U 1 1 68680761 +P 5150 3300 +F 0 "U8" H 5150 3300 60 0000 C CNN +F 1 "d_or" H 5150 3400 60 0000 C CNN +F 2 "" H 5150 3300 60 0000 C CNN +F 3 "" H 5150 3300 60 0000 C CNN + 1 5150 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U5 +U 1 1 68680769 +P 4100 3650 +F 0 "U5" H 4100 3650 60 0000 C CNN +F 1 "d_or" H 4100 3750 60 0000 C CNN +F 2 "" H 4100 3650 60 0000 C CNN +F 3 "" H 4100 3650 60 0000 C CNN + 1 4100 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_or U9 +U 1 1 6868076F +P 5150 3900 +F 0 "U9" H 5150 3900 60 0000 C CNN +F 1 "d_or" H 5150 4000 60 0000 C CNN +F 2 "" H 5150 3900 60 0000 C CNN +F 3 "" H 5150 3900 60 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 686808D4 +P 6200 1650 +F 0 "U10" H 6200 1550 60 0000 C CNN +F 1 "d_inverter" H 6200 1800 60 0000 C CNN +F 2 "" H 6250 1600 60 0000 C CNN +F 3 "" H 6250 1600 60 0000 C CNN + 1 6200 1650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 68680929 +P 6200 2350 +F 0 "U11" H 6200 2250 60 0000 C CNN +F 1 "d_inverter" H 6200 2500 60 0000 C CNN +F 2 "" H 6250 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 1 6200 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6868096E +P 6200 2950 +F 0 "U12" H 6200 2850 60 0000 C CNN +F 1 "d_inverter" H 6200 3100 60 0000 C CNN +F 2 "" H 6250 2900 60 0000 C CNN +F 3 "" H 6250 2900 60 0000 C CNN + 1 6200 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 686809B9 +P 6200 3600 +F 0 "U13" H 6200 3500 60 0000 C CNN +F 1 "d_inverter" H 6200 3750 60 0000 C CNN +F 2 "" H 6250 3550 60 0000 C CNN +F 3 "" H 6250 3550 60 0000 C CNN + 1 6200 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 3600 5900 3600 +Wire Wire Line + 5600 3850 5600 3600 +Wire Wire Line + 5600 2950 5900 2950 +Wire Wire Line + 5600 3250 5600 2950 +Wire Wire Line + 5600 2350 5900 2350 +Wire Wire Line + 5600 2600 5600 2350 +Wire Wire Line + 5600 1650 5900 1650 +Wire Wire Line + 5600 2000 5600 1650 +Wire Wire Line + 2850 3900 4700 3900 +Wire Wire Line + 2850 3300 4700 3300 +Wire Wire Line + 2850 2650 4700 2650 +Wire Wire Line + 2850 2050 4700 2050 +Wire Wire Line + 4550 3800 4700 3800 +Wire Wire Line + 4550 3600 4550 3800 +Wire Wire Line + 4550 3200 4700 3200 +Wire Wire Line + 4550 3000 4550 3200 +Wire Wire Line + 4550 2550 4700 2550 +Wire Wire Line + 4550 2350 4550 2550 +Wire Wire Line + 4550 1950 4700 1950 +Wire Wire Line + 4550 1750 4550 1950 +$Comp +L d_or U14 +U 1 1 68680CEF +P 4100 4350 +F 0 "U14" H 4100 4350 60 0000 C CNN +F 1 "d_or" H 4100 4450 60 0000 C CNN +F 2 "" H 4100 4350 60 0000 C CNN +F 3 "" H 4100 4350 60 0000 C CNN + 1 4100 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U15 +U 1 1 68680CF5 +P 5150 4600 +F 0 "U15" H 5150 4600 60 0000 C CNN +F 1 "d_or" H 5150 4700 60 0000 C CNN +F 2 "" H 5150 4600 60 0000 C CNN +F 3 "" H 5150 4600 60 0000 C CNN + 1 5150 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2850 4600 4700 4600 +Wire Wire Line + 4550 4500 4700 4500 +Wire Wire Line + 4550 4300 4550 4500 +$Comp +L d_inverter U16 +U 1 1 68680D10 +P 6200 4250 +F 0 "U16" H 6200 4150 60 0000 C CNN +F 1 "d_inverter" H 6200 4400 60 0000 C CNN +F 2 "" H 6250 4200 60 0000 C CNN +F 3 "" H 6250 4200 60 0000 C CNN + 1 6200 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 4550 5600 4250 +Wire Wire Line + 5600 4250 5900 4250 +$Comp +L d_buffer U17 +U 1 1 68680DA0 +P 2200 5350 +F 0 "U17" H 2200 5300 60 0000 C CNN +F 1 "d_buffer" H 2200 5400 60 0000 C CNN +F 2 "" H 2200 5350 60 0000 C CNN +F 3 "" H 2200 5350 60 0000 C CNN + 1 2200 5350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2850 5350 2850 2050 +Connection ~ 2850 2650 +Connection ~ 2850 3300 +Connection ~ 2850 3900 +Connection ~ 2850 4600 +$Comp +L PORT U1 +U 1 1 686810B2 +P 2250 4400 +F 0 "U1" H 2300 4500 30 0000 C CNN +F 1 "PORT" H 2250 4400 30 0000 C CNN +F 2 "" H 2250 4400 60 0000 C CNN +F 3 "" H 2250 4400 60 0000 C CNN + 1 2250 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 4400 3650 4400 +Wire Wire Line + 3650 4400 3650 4350 +$Comp +L PORT U1 +U 2 1 6868124C +P 7150 4500 +F 0 "U1" H 7200 4600 30 0000 C CNN +F 1 "PORT" H 7150 4500 30 0000 C CNN +F 2 "" H 7150 4500 60 0000 C CNN +F 3 "" H 7150 4500 60 0000 C CNN + 2 7150 4500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 6868133D +P 7150 4250 +F 0 "U1" H 7200 4350 30 0000 C CNN +F 1 "PORT" H 7150 4250 30 0000 C CNN +F 2 "" H 7150 4250 60 0000 C CNN +F 3 "" H 7150 4250 60 0000 C CNN + 3 7150 4250 + -1 0 0 1 +$EndComp +Wire Wire Line + 6500 4250 6900 4250 +Wire Wire Line + 6900 4500 5600 4500 +Connection ~ 5600 4500 +$Comp +L PORT U1 +U 4 1 686814AF +P 7200 3600 +F 0 "U1" H 7250 3700 30 0000 C CNN +F 1 "PORT" H 7200 3600 30 0000 C CNN +F 2 "" H 7200 3600 60 0000 C CNN +F 3 "" H 7200 3600 60 0000 C CNN + 4 7200 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 68681516 +P 7200 3800 +F 0 "U1" H 7250 3900 30 0000 C CNN +F 1 "PORT" H 7200 3800 30 0000 C CNN +F 2 "" H 7200 3800 60 0000 C CNN +F 3 "" H 7200 3800 60 0000 C CNN + 5 7200 3800 + -1 0 0 1 +$EndComp +Wire Wire Line + 6500 3600 6950 3600 +Wire Wire Line + 6950 3800 5600 3800 +Connection ~ 5600 3800 +$Comp +L PORT U1 +U 8 1 686816C8 +P 7250 2950 +F 0 "U1" H 7300 3050 30 0000 C CNN +F 1 "PORT" H 7250 2950 30 0000 C CNN +F 2 "" H 7250 2950 60 0000 C CNN +F 3 "" H 7250 2950 60 0000 C CNN + 8 7250 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 6868172D +P 7250 3150 +F 0 "U1" H 7300 3250 30 0000 C CNN +F 1 "PORT" H 7250 3150 30 0000 C CNN +F 2 "" H 7250 3150 60 0000 C CNN +F 3 "" H 7250 3150 60 0000 C CNN + 9 7250 3150 + -1 0 0 1 +$EndComp +Wire Wire Line + 6500 2950 7000 2950 +Wire Wire Line + 7000 3150 5600 3150 +Connection ~ 5600 3150 +$Comp +L PORT U1 +U 10 1 68681826 +P 7050 2550 +F 0 "U1" H 7100 2650 30 0000 C CNN +F 1 "PORT" H 7050 2550 30 0000 C CNN +F 2 "" H 7050 2550 60 0000 C CNN +F 3 "" H 7050 2550 60 0000 C CNN + 10 7050 2550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 68681885 +P 7050 2350 +F 0 "U1" H 7100 2450 30 0000 C CNN +F 1 "PORT" H 7050 2350 30 0000 C CNN +F 2 "" H 7050 2350 60 0000 C CNN +F 3 "" H 7050 2350 60 0000 C CNN + 11 7050 2350 + -1 0 0 1 +$EndComp +Wire Wire Line + 6500 2350 6800 2350 +Wire Wire Line + 6800 2550 5600 2550 +Connection ~ 5600 2550 +$Comp +L PORT U1 +U 12 1 686819AB +P 7100 1650 +F 0 "U1" H 7150 1750 30 0000 C CNN +F 1 "PORT" H 7100 1650 30 0000 C CNN +F 2 "" H 7100 1650 60 0000 C CNN +F 3 "" H 7100 1650 60 0000 C CNN + 12 7100 1650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 68681A0A +P 7100 1900 +F 0 "U1" H 7150 2000 30 0000 C CNN +F 1 "PORT" H 7100 1900 30 0000 C CNN +F 2 "" H 7100 1900 60 0000 C CNN +F 3 "" H 7100 1900 60 0000 C CNN + 13 7100 1900 + -1 0 0 1 +$EndComp +Wire Wire Line + 6500 1650 6850 1650 +Wire Wire Line + 6850 1900 5600 1900 +Connection ~ 5600 1900 +$Comp +L PORT U1 +U 14 1 68681BBA +P 2300 1600 +F 0 "U1" H 2350 1700 30 0000 C CNN +F 1 "PORT" H 2300 1600 30 0000 C CNN +F 2 "" H 2300 1600 60 0000 C CNN +F 3 "" H 2300 1600 60 0000 C CNN + 14 2300 1600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 68681C37 +P 2300 1850 +F 0 "U1" H 2350 1950 30 0000 C CNN +F 1 "PORT" H 2300 1850 30 0000 C CNN +F 2 "" H 2300 1850 60 0000 C CNN +F 3 "" H 2300 1850 60 0000 C CNN + 15 2300 1850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2550 1600 3650 1600 +Wire Wire Line + 3650 1600 3650 1700 +Wire Wire Line + 3650 1800 3650 1850 +Wire Wire Line + 3650 1850 2550 1850 +$Comp +L PORT U1 +U 16 1 68681E20 +P 2250 2200 +F 0 "U1" H 2300 2300 30 0000 C CNN +F 1 "PORT" H 2250 2200 30 0000 C CNN +F 2 "" H 2250 2200 60 0000 C CNN +F 3 "" H 2250 2200 60 0000 C CNN + 16 2250 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 17 1 68681E81 +P 2250 2450 +F 0 "U1" H 2300 2550 30 0000 C CNN +F 1 "PORT" H 2250 2450 30 0000 C CNN +F 2 "" H 2250 2450 60 0000 C CNN +F 3 "" H 2250 2450 60 0000 C CNN + 17 2250 2450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 2200 3650 2200 +Wire Wire Line + 3650 2200 3650 2300 +Wire Wire Line + 3650 2400 3650 2450 +Wire Wire Line + 3650 2450 2500 2450 +$Comp +L PORT U1 +U 20 1 68682086 +P 2250 2900 +F 0 "U1" H 2300 3000 30 0000 C CNN +F 1 "PORT" H 2250 2900 30 0000 C CNN +F 2 "" H 2250 2900 60 0000 C CNN +F 3 "" H 2250 2900 60 0000 C CNN + 20 2250 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 21 1 686820F1 +P 2250 3100 +F 0 "U1" H 2300 3200 30 0000 C CNN +F 1 "PORT" H 2250 3100 30 0000 C CNN +F 2 "" H 2250 3100 60 0000 C CNN +F 3 "" H 2250 3100 60 0000 C CNN + 21 2250 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 2900 3650 2900 +Wire Wire Line + 3650 2900 3650 2950 +Wire Wire Line + 3650 3050 3650 3100 +Wire Wire Line + 3650 3100 2500 3100 +$Comp +L PORT U1 +U 22 1 68682267 +P 2300 3500 +F 0 "U1" H 2350 3600 30 0000 C CNN +F 1 "PORT" H 2300 3500 30 0000 C CNN +F 2 "" H 2300 3500 60 0000 C CNN +F 3 "" H 2300 3500 60 0000 C CNN + 22 2300 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 23 1 68682310 +P 2300 3700 +F 0 "U1" H 2350 3800 30 0000 C CNN +F 1 "PORT" H 2300 3700 30 0000 C CNN +F 2 "" H 2300 3700 60 0000 C CNN +F 3 "" H 2300 3700 60 0000 C CNN + 23 2300 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 24 1 68682390 +P 2250 4150 +F 0 "U1" H 2300 4250 30 0000 C CNN +F 1 "PORT" H 2250 4150 30 0000 C CNN +F 2 "" H 2250 4150 60 0000 C CNN +F 3 "" H 2250 4150 60 0000 C CNN + 24 2250 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2550 3500 3650 3500 +Wire Wire Line + 3650 3500 3650 3550 +Wire Wire Line + 3650 3650 3650 3700 +Wire Wire Line + 3650 3700 2550 3700 +Wire Wire Line + 2500 4150 3650 4150 +Wire Wire Line + 3650 4150 3650 4250 +$Comp +L PORT U1 +U 19 1 68682BB8 +P 1350 5350 +F 0 "U1" H 1400 5450 30 0000 C CNN +F 1 "PORT" H 1350 5350 30 0000 C CNN +F 2 "" H 1350 5350 60 0000 C CNN +F 3 "" H 1350 5350 60 0000 C CNN + 19 1350 5350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1600 5350 1700 5350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/f100102/f100102.sub b/library/SubcircuitLibrary/f100102/f100102.sub new file mode 100644 index 000000000..e1f542189 --- /dev/null +++ b/library/SubcircuitLibrary/f100102/f100102.sub @@ -0,0 +1,70 @@ +* Subcircuit f100102 +.subckt f100102 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ +* c:\fossee\esim\library\subcircuitlibrary\f100102\f100102.cir +* u2 net-_u1-pad14_ net-_u1-pad15_ net-_u2-pad3_ d_or +* u6 net-_u2-pad3_ net-_u15-pad2_ net-_u1-pad13_ d_or +* u3 net-_u1-pad16_ net-_u1-pad17_ net-_u3-pad3_ d_or +* u7 net-_u3-pad3_ net-_u15-pad2_ net-_u1-pad10_ d_or +* u4 net-_u1-pad20_ net-_u1-pad21_ net-_u4-pad3_ d_or +* u8 net-_u4-pad3_ net-_u15-pad2_ net-_u1-pad9_ d_or +* u5 net-_u1-pad22_ net-_u1-pad23_ net-_u5-pad3_ d_or +* u9 net-_u5-pad3_ net-_u15-pad2_ net-_u1-pad5_ d_or +* u10 net-_u1-pad13_ net-_u1-pad12_ d_inverter +* u11 net-_u1-pad10_ net-_u1-pad11_ d_inverter +* u12 net-_u1-pad9_ net-_u1-pad8_ d_inverter +* u13 net-_u1-pad5_ net-_u1-pad4_ d_inverter +* u14 net-_u1-pad24_ net-_u1-pad1_ net-_u14-pad3_ d_or +* u15 net-_u14-pad3_ net-_u15-pad2_ net-_u1-pad2_ d_or +* u16 net-_u1-pad2_ net-_u1-pad3_ d_inverter +* u17 net-_u1-pad19_ net-_u15-pad2_ d_buffer +a1 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u15-pad2_ ] net-_u1-pad13_ u6 +a3 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ net-_u15-pad2_ ] net-_u1-pad10_ u7 +a5 [net-_u1-pad20_ net-_u1-pad21_ ] net-_u4-pad3_ u4 +a6 [net-_u4-pad3_ net-_u15-pad2_ ] net-_u1-pad9_ u8 +a7 [net-_u1-pad22_ net-_u1-pad23_ ] net-_u5-pad3_ u5 +a8 [net-_u5-pad3_ net-_u15-pad2_ ] net-_u1-pad5_ u9 +a9 net-_u1-pad13_ net-_u1-pad12_ u10 +a10 net-_u1-pad10_ net-_u1-pad11_ u11 +a11 net-_u1-pad9_ net-_u1-pad8_ u12 +a12 net-_u1-pad5_ net-_u1-pad4_ u13 +a13 [net-_u1-pad24_ net-_u1-pad1_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u15-pad2_ ] net-_u1-pad2_ u15 +a15 net-_u1-pad2_ net-_u1-pad3_ u16 +a16 net-_u1-pad19_ net-_u15-pad2_ u17 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends f100102 \ No newline at end of file diff --git a/library/SubcircuitLibrary/f100102/f100102_Previous_Values.xml b/library/SubcircuitLibrary/f100102/f100102_Previous_Values.xml new file mode 100644 index 000000000..178b9dab8 --- /dev/null +++ b/library/SubcircuitLibrary/f100102/f100102_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecd_ord_ord_ord_ord_ord_ord_ord_ord_inverterd_inverterd_inverterd_inverterd_ord_ord_inverterd_buffer \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic100117/3_and-cache.lib b/library/SubcircuitLibrary/ic100117/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ic100117/3_and.cir b/library/SubcircuitLibrary/ic100117/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/ic100117/3_and.cir.out b/library/SubcircuitLibrary/ic100117/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ic100117/3_and.pro b/library/SubcircuitLibrary/ic100117/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/ic100117/3_and.sch b/library/SubcircuitLibrary/ic100117/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ic100117/3_and.sub b/library/SubcircuitLibrary/ic100117/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic100117/3_and_Previous_Values.xml b/library/SubcircuitLibrary/ic100117/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic100117/analysis b/library/SubcircuitLibrary/ic100117/analysis new file mode 100644 index 000000000..eed5e2985 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/analysis @@ -0,0 +1 @@ +.tran 250e-03 20e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic100117/ic100117-cache.lib b/library/SubcircuitLibrary/ic100117/ic100117-cache.lib new file mode 100644 index 000000000..ee93e1956 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/ic100117-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ic100117/ic100117.cir b/library/SubcircuitLibrary/ic100117/ic100117.cir new file mode 100644 index 000000000..e11bd03ad --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/ic100117.cir @@ -0,0 +1,23 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\ic100117\ic100117.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/10/25 22:41:29 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U5-Pad3_ d_or +U6 Net-_U1-Pad24_ Net-_U1-Pad1_ Net-_U6-Pad3_ d_or +X3 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U1-Pad19_ Net-_U1-Pad4_ 3_and +U9 Net-_U1-Pad4_ Net-_U1-Pad5_ d_inverter +U10 Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U10-Pad3_ d_or +U2 Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U2-Pad3_ d_or +X1 Net-_U10-Pad3_ Net-_U2-Pad3_ Net-_U1-Pad17_ Net-_U1-Pad8_ 3_and +U7 Net-_U1-Pad8_ Net-_U1-Pad9_ d_inverter +U3 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U3-Pad3_ d_or +U4 Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U4-Pad3_ d_or +X2 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad16_ Net-_U1-Pad11_ 3_and +U8 Net-_U1-Pad11_ Net-_U1-Pad10_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad24_ PORT + +.end diff --git a/library/SubcircuitLibrary/ic100117/ic100117.cir.out b/library/SubcircuitLibrary/ic100117/ic100117.cir.out new file mode 100644 index 000000000..b989016d0 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/ic100117.cir.out @@ -0,0 +1,52 @@ +* c:\fossee\esim\library\subcircuitlibrary\ic100117\ic100117.cir + +.include 3_and.sub +* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_or +* u6 net-_u1-pad24_ net-_u1-pad1_ net-_u6-pad3_ d_or +x3 net-_u5-pad3_ net-_u6-pad3_ net-_u1-pad19_ net-_u1-pad4_ 3_and +* u9 net-_u1-pad4_ net-_u1-pad5_ d_inverter +* u10 net-_u1-pad22_ net-_u1-pad23_ net-_u10-pad3_ d_or +* u2 net-_u1-pad20_ net-_u1-pad21_ net-_u2-pad3_ d_or +x1 net-_u10-pad3_ net-_u2-pad3_ net-_u1-pad17_ net-_u1-pad8_ 3_and +* u7 net-_u1-pad8_ net-_u1-pad9_ d_inverter +* u3 net-_u1-pad12_ net-_u1-pad13_ net-_u3-pad3_ d_or +* u4 net-_u1-pad14_ net-_u1-pad15_ net-_u4-pad3_ d_or +x2 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad16_ net-_u1-pad11_ 3_and +* u8 net-_u1-pad11_ net-_u1-pad10_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ port +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5 +a2 [net-_u1-pad24_ net-_u1-pad1_ ] net-_u6-pad3_ u6 +a3 net-_u1-pad4_ net-_u1-pad5_ u9 +a4 [net-_u1-pad22_ net-_u1-pad23_ ] net-_u10-pad3_ u10 +a5 [net-_u1-pad20_ net-_u1-pad21_ ] net-_u2-pad3_ u2 +a6 net-_u1-pad8_ net-_u1-pad9_ u7 +a7 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u4-pad3_ u4 +a9 net-_u1-pad11_ net-_u1-pad10_ u8 +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 250e-03 20e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ic100117/ic100117.pro b/library/SubcircuitLibrary/ic100117/ic100117.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/ic100117.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ic100117/ic100117.sch b/library/SubcircuitLibrary/ic100117/ic100117.sch new file mode 100644 index 000000000..eab919cf8 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/ic100117.sch @@ -0,0 +1,506 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U5 +U 1 1 686FF152 +P 4250 2550 +F 0 "U5" H 4250 2550 60 0000 C CNN +F 1 "d_or" H 4250 2650 60 0000 C CNN +F 2 "" H 4250 2550 60 0000 C CNN +F 3 "" H 4250 2550 60 0000 C CNN + 1 4250 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 686FF177 +P 4250 3000 +F 0 "U6" H 4250 3000 60 0000 C CNN +F 1 "d_or" H 4250 3100 60 0000 C CNN +F 2 "" H 4250 3000 60 0000 C CNN +F 3 "" H 4250 3000 60 0000 C CNN + 1 4250 3000 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 686FF19E +P 5550 2750 +F 0 "X3" H 5650 2700 60 0000 C CNN +F 1 "3_and" H 5700 2900 60 0000 C CNN +F 2 "" H 5550 2750 60 0000 C CNN +F 3 "" H 5550 2750 60 0000 C CNN + 1 5550 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 686FF1F7 +P 6900 2700 +F 0 "U9" H 6900 2600 60 0000 C CNN +F 1 "d_inverter" H 6900 2850 60 0000 C CNN +F 2 "" H 6950 2650 60 0000 C CNN +F 3 "" H 6950 2650 60 0000 C CNN + 1 6900 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 2500 5200 2500 +Wire Wire Line + 5200 2500 5200 2600 +Wire Wire Line + 4700 2950 4700 2700 +Wire Wire Line + 4700 2700 5200 2700 +Wire Wire Line + 5200 3250 5200 2800 +Wire Wire Line + 3350 3250 5200 3250 +Wire Wire Line + 6050 2700 6600 2700 +Wire Wire Line + 6300 2700 6300 3150 +Wire Wire Line + 6300 3150 7450 3150 +Connection ~ 6300 2700 +$Comp +L d_or U10 +U 1 1 686FF420 +P 4150 3750 +F 0 "U10" H 4150 3750 60 0000 C CNN +F 1 "d_or" H 4150 3850 60 0000 C CNN +F 2 "" H 4150 3750 60 0000 C CNN +F 3 "" H 4150 3750 60 0000 C CNN + 1 4150 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U2 +U 1 1 686FF426 +P 4150 4200 +F 0 "U2" H 4150 4200 60 0000 C CNN +F 1 "d_or" H 4150 4300 60 0000 C CNN +F 2 "" H 4150 4200 60 0000 C CNN +F 3 "" H 4150 4200 60 0000 C CNN + 1 4150 4200 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 686FF42C +P 5450 3950 +F 0 "X1" H 5550 3900 60 0000 C CNN +F 1 "3_and" H 5600 4100 60 0000 C CNN +F 2 "" H 5450 3950 60 0000 C CNN +F 3 "" H 5450 3950 60 0000 C CNN + 1 5450 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 686FF432 +P 6800 3900 +F 0 "U7" H 6800 3800 60 0000 C CNN +F 1 "d_inverter" H 6800 4050 60 0000 C CNN +F 2 "" H 6850 3850 60 0000 C CNN +F 3 "" H 6850 3850 60 0000 C CNN + 1 6800 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4600 3700 5100 3700 +Wire Wire Line + 5100 3700 5100 3800 +Wire Wire Line + 4600 4150 4600 3900 +Wire Wire Line + 4600 3900 5100 3900 +Wire Wire Line + 5100 4450 5100 4000 +Wire Wire Line + 3400 4450 5100 4450 +Wire Wire Line + 5950 3900 6500 3900 +Wire Wire Line + 6200 3900 6200 4350 +Wire Wire Line + 6200 4350 7400 4350 +Connection ~ 6200 3900 +$Comp +L d_or U3 +U 1 1 686FF4EE +P 4150 4900 +F 0 "U3" H 4150 4900 60 0000 C CNN +F 1 "d_or" H 4150 5000 60 0000 C CNN +F 2 "" H 4150 4900 60 0000 C CNN +F 3 "" H 4150 4900 60 0000 C CNN + 1 4150 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 686FF4F4 +P 4150 5350 +F 0 "U4" H 4150 5350 60 0000 C CNN +F 1 "d_or" H 4150 5450 60 0000 C CNN +F 2 "" H 4150 5350 60 0000 C CNN +F 3 "" H 4150 5350 60 0000 C CNN + 1 4150 5350 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 686FF4FA +P 5450 5100 +F 0 "X2" H 5550 5050 60 0000 C CNN +F 1 "3_and" H 5600 5250 60 0000 C CNN +F 2 "" H 5450 5100 60 0000 C CNN +F 3 "" H 5450 5100 60 0000 C CNN + 1 5450 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 686FF500 +P 6800 5050 +F 0 "U8" H 6800 4950 60 0000 C CNN +F 1 "d_inverter" H 6800 5200 60 0000 C CNN +F 2 "" H 6850 5000 60 0000 C CNN +F 3 "" H 6850 5000 60 0000 C CNN + 1 6800 5050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4600 4850 5100 4850 +Wire Wire Line + 5100 4850 5100 4950 +Wire Wire Line + 4600 5300 4600 5050 +Wire Wire Line + 4600 5050 5100 5050 +Wire Wire Line + 5100 5600 5100 5150 +Wire Wire Line + 3350 5600 5100 5600 +Wire Wire Line + 5950 5050 6500 5050 +Wire Wire Line + 6200 5050 6200 5500 +Wire Wire Line + 6200 5500 7450 5500 +Connection ~ 6200 5050 +$Comp +L PORT U1 +U 1 1 686FF57E +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 1 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 686FF5CF +P 3100 2450 +F 0 "U1" H 3150 2550 30 0000 C CNN +F 1 "PORT" H 3100 2450 30 0000 C CNN +F 2 "" H 3100 2450 60 0000 C CNN +F 3 "" H 3100 2450 60 0000 C CNN + 2 3100 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 686FF67C +P 2750 2550 +F 0 "U1" H 2800 2650 30 0000 C CNN +F 1 "PORT" H 2750 2550 30 0000 C CNN +F 2 "" H 2750 2550 60 0000 C CNN +F 3 "" H 2750 2550 60 0000 C CNN + 3 2750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 686FF6C9 +P 7700 3150 +F 0 "U1" H 7750 3250 30 0000 C CNN +F 1 "PORT" H 7700 3150 30 0000 C CNN +F 2 "" H 7700 3150 60 0000 C CNN +F 3 "" H 7700 3150 60 0000 C CNN + 4 7700 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 686FF7B4 +P 7700 2700 +F 0 "U1" H 7750 2800 30 0000 C CNN +F 1 "PORT" H 7700 2700 30 0000 C CNN +F 2 "" H 7700 2700 60 0000 C CNN +F 3 "" H 7700 2700 60 0000 C CNN + 5 7700 2700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 686FF8EF +P 7650 4350 +F 0 "U1" H 7700 4450 30 0000 C CNN +F 1 "PORT" H 7650 4350 30 0000 C CNN +F 2 "" H 7650 4350 60 0000 C CNN +F 3 "" H 7650 4350 60 0000 C CNN + 8 7650 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 686FFA28 +P 7650 3900 +F 0 "U1" H 7700 4000 30 0000 C CNN +F 1 "PORT" H 7650 3900 30 0000 C CNN +F 2 "" H 7650 3900 60 0000 C CNN +F 3 "" H 7650 3900 60 0000 C CNN + 9 7650 3900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 686FFA7D +P 7700 5050 +F 0 "U1" H 7750 5150 30 0000 C CNN +F 1 "PORT" H 7700 5050 30 0000 C CNN +F 2 "" H 7700 5050 60 0000 C CNN +F 3 "" H 7700 5050 60 0000 C CNN + 10 7700 5050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 686FFB76 +P 7700 5500 +F 0 "U1" H 7750 5600 30 0000 C CNN +F 1 "PORT" H 7700 5500 30 0000 C CNN +F 2 "" H 7700 5500 60 0000 C CNN +F 3 "" H 7700 5500 60 0000 C CNN + 11 7700 5500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 686FFBC3 +P 3150 4800 +F 0 "U1" H 3200 4900 30 0000 C CNN +F 1 "PORT" H 3150 4800 30 0000 C CNN +F 2 "" H 3150 4800 60 0000 C CNN +F 3 "" H 3150 4800 60 0000 C CNN + 12 3150 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 686FFD46 +P 2850 4900 +F 0 "U1" H 2900 5000 30 0000 C CNN +F 1 "PORT" H 2850 4900 30 0000 C CNN +F 2 "" H 2850 4900 60 0000 C CNN +F 3 "" H 2850 4900 60 0000 C CNN + 13 2850 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 686FFDC4 +P 3150 5250 +F 0 "U1" H 3200 5350 30 0000 C CNN +F 1 "PORT" H 3150 5250 30 0000 C CNN +F 2 "" H 3150 5250 60 0000 C CNN +F 3 "" H 3150 5250 60 0000 C CNN + 14 3150 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 686FFE4F +P 2800 5350 +F 0 "U1" H 2850 5450 30 0000 C CNN +F 1 "PORT" H 2800 5350 30 0000 C CNN +F 2 "" H 2800 5350 60 0000 C CNN +F 3 "" H 2800 5350 60 0000 C CNN + 15 2800 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 686FFEA4 +P 3100 5600 +F 0 "U1" H 3150 5700 30 0000 C CNN +F 1 "PORT" H 3100 5600 30 0000 C CNN +F 2 "" H 3100 5600 60 0000 C CNN +F 3 "" H 3100 5600 60 0000 C CNN + 16 3100 5600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 17 1 686FFF0B +P 3150 4450 +F 0 "U1" H 3200 4550 30 0000 C CNN +F 1 "PORT" H 3150 4450 30 0000 C CNN +F 2 "" H 3150 4450 60 0000 C CNN +F 3 "" H 3150 4450 60 0000 C CNN + 17 3150 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 19 1 6870003B +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 19 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 20 1 68700186 +P 3000 4100 +F 0 "U1" H 3050 4200 30 0000 C CNN +F 1 "PORT" H 3000 4100 30 0000 C CNN +F 2 "" H 3000 4100 60 0000 C CNN +F 3 "" H 3000 4100 60 0000 C CNN + 20 3000 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 21 1 6870025E +P 2800 4200 +F 0 "U1" H 2850 4300 30 0000 C CNN +F 1 "PORT" H 2800 4200 30 0000 C CNN +F 2 "" H 2800 4200 60 0000 C CNN +F 3 "" H 2800 4200 60 0000 C CNN + 21 2800 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 22 1 687002CF +P 3100 3650 +F 0 "U1" H 3150 3750 30 0000 C CNN +F 1 "PORT" H 3100 3650 30 0000 C CNN +F 2 "" H 3100 3650 60 0000 C CNN +F 3 "" H 3100 3650 60 0000 C CNN + 22 3100 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 23 1 68700328 +P 2850 3750 +F 0 "U1" H 2900 3850 30 0000 C CNN +F 1 "PORT" H 2850 3750 30 0000 C CNN +F 2 "" H 2850 3750 60 0000 C CNN +F 3 "" H 2850 3750 60 0000 C CNN + 23 2850 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 24 1 6870038D +P 2700 2900 +F 0 "U1" H 2750 3000 30 0000 C CNN +F 1 "PORT" H 2700 2900 30 0000 C CNN +F 2 "" H 2700 2900 60 0000 C CNN +F 3 "" H 2700 2900 60 0000 C CNN + 24 2700 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 2450 3800 2450 +Wire Wire Line + 3800 2550 3000 2550 +Wire Wire Line + 3800 2900 2950 2900 +Wire Wire Line + 3350 3000 3800 3000 +Wire Wire Line + 3350 3650 3700 3650 +Wire Wire Line + 3700 3750 3100 3750 +Wire Wire Line + 3250 4100 3700 4100 +Wire Wire Line + 3700 4200 3050 4200 +Wire Wire Line + 3700 4800 3400 4800 +Wire Wire Line + 3700 4900 3100 4900 +Wire Wire Line + 3700 5250 3400 5250 +Wire Wire Line + 3700 5350 3050 5350 +Wire Wire Line + 7200 2700 7450 2700 +Wire Wire Line + 7400 3900 7100 3900 +Wire Wire Line + 7450 5050 7100 5050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ic100117/ic100117.sub b/library/SubcircuitLibrary/ic100117/ic100117.sub new file mode 100644 index 000000000..5ceb0b370 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/ic100117.sub @@ -0,0 +1,46 @@ +* Subcircuit ic100117 +.subckt ic100117 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ +* c:\fossee\esim\library\subcircuitlibrary\ic100117\ic100117.cir +.include 3_and.sub +* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_or +* u6 net-_u1-pad24_ net-_u1-pad1_ net-_u6-pad3_ d_or +x3 net-_u5-pad3_ net-_u6-pad3_ net-_u1-pad19_ net-_u1-pad4_ 3_and +* u9 net-_u1-pad4_ net-_u1-pad5_ d_inverter +* u10 net-_u1-pad22_ net-_u1-pad23_ net-_u10-pad3_ d_or +* u2 net-_u1-pad20_ net-_u1-pad21_ net-_u2-pad3_ d_or +x1 net-_u10-pad3_ net-_u2-pad3_ net-_u1-pad17_ net-_u1-pad8_ 3_and +* u7 net-_u1-pad8_ net-_u1-pad9_ d_inverter +* u3 net-_u1-pad12_ net-_u1-pad13_ net-_u3-pad3_ d_or +* u4 net-_u1-pad14_ net-_u1-pad15_ net-_u4-pad3_ d_or +x2 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad16_ net-_u1-pad11_ 3_and +* u8 net-_u1-pad11_ net-_u1-pad10_ d_inverter +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5 +a2 [net-_u1-pad24_ net-_u1-pad1_ ] net-_u6-pad3_ u6 +a3 net-_u1-pad4_ net-_u1-pad5_ u9 +a4 [net-_u1-pad22_ net-_u1-pad23_ ] net-_u10-pad3_ u10 +a5 [net-_u1-pad20_ net-_u1-pad21_ ] net-_u2-pad3_ u2 +a6 net-_u1-pad8_ net-_u1-pad9_ u7 +a7 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u4-pad3_ u4 +a9 net-_u1-pad11_ net-_u1-pad10_ u8 +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends ic100117 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic100117/ic100117_Previous_Values.xml b/library/SubcircuitLibrary/ic100117/ic100117_Previous_Values.xml new file mode 100644 index 000000000..3e80f3732 --- /dev/null +++ b/library/SubcircuitLibrary/ic100117/ic100117_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_inverterd_ord_ord_inverterd_ord_ord_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025020secmssec \ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1496/NPN.lib b/library/SubcircuitLibrary/mc1496/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/mc1496/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/mc1496/analysis b/library/SubcircuitLibrary/mc1496/analysis new file mode 100644 index 000000000..6dcba7452 --- /dev/null +++ b/library/SubcircuitLibrary/mc1496/analysis @@ -0,0 +1 @@ +.tran 0.1e-06 10e-03 0e-03 \ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1496/mc1496-cache.lib b/library/SubcircuitLibrary/mc1496/mc1496-cache.lib new file mode 100644 index 000000000..e95e63c62 --- /dev/null +++ b/library/SubcircuitLibrary/mc1496/mc1496-cache.lib @@ -0,0 +1,83 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1496/mc1496.cir b/library/SubcircuitLibrary/mc1496/mc1496.cir new file mode 100644 index 000000000..b9067a27b --- /dev/null +++ b/library/SubcircuitLibrary/mc1496/mc1496.cir @@ -0,0 +1,23 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1496\mc1496.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/12/25 22:39:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q2-Pad1_ Net-_Q5-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q9 Net-_Q5-Pad1_ Net-_Q2-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q3 Net-_Q2-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q3-Pad3_ Net-_Q1-Pad1_ Net-_Q4-Pad3_ eSim_NPN +Q7 Net-_Q6-Pad3_ Net-_Q7-Pad2_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q1-Pad1_ Net-_Q8-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad3_ eSim_NPN +R2 Net-_Q4-Pad3_ Net-_R1-Pad2_ 500 +R1 Net-_Q1-Pad3_ Net-_R1-Pad2_ 500 +R3 Net-_Q8-Pad3_ Net-_R1-Pad2_ 500 +U1 Net-_Q7-Pad2_ Net-_Q7-Pad3_ Net-_Q3-Pad3_ Net-_Q3-Pad2_ Net-_Q1-Pad1_ Net-_Q2-Pad1_ ? Net-_Q2-Pad2_ ? Net-_Q5-Pad2_ ? Net-_Q5-Pad1_ ? Net-_R1-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/mc1496/mc1496.cir.out b/library/SubcircuitLibrary/mc1496/mc1496.cir.out new file mode 100644 index 000000000..c0008ca7c --- /dev/null +++ b/library/SubcircuitLibrary/mc1496/mc1496.cir.out @@ -0,0 +1,25 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1496\mc1496.cir + +.include NPN.lib +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q5-pad2_ net-_q2-pad3_ Q2N2222 +q6 net-_q2-pad1_ net-_q5-pad2_ net-_q6-pad3_ Q2N2222 +q9 net-_q5-pad1_ net-_q2-pad2_ net-_q6-pad3_ Q2N2222 +q3 net-_q2-pad3_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q4 net-_q3-pad3_ net-_q1-pad1_ net-_q4-pad3_ Q2N2222 +q7 net-_q6-pad3_ net-_q7-pad2_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q1-pad1_ net-_q8-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2222 +r2 net-_q4-pad3_ net-_r1-pad2_ 500 +r1 net-_q1-pad3_ net-_r1-pad2_ 500 +r3 net-_q8-pad3_ net-_r1-pad2_ 500 +* u1 net-_q7-pad2_ net-_q7-pad3_ net-_q3-pad3_ net-_q3-pad2_ net-_q1-pad1_ net-_q2-pad1_ ? net-_q2-pad2_ ? net-_q5-pad2_ ? net-_q5-pad1_ ? net-_r1-pad2_ port +.tran 0.1e-06 10e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1496/mc1496.pro b/library/SubcircuitLibrary/mc1496/mc1496.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/mc1496/mc1496.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1496/mc1496.sch b/library/SubcircuitLibrary/mc1496/mc1496.sch new file mode 100644 index 000000000..f020d21a7 --- /dev/null +++ b/library/SubcircuitLibrary/mc1496/mc1496.sch @@ -0,0 +1,442 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:mc1496-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 684ADEF2 +P 5350 2400 +F 0 "Q2" H 5250 2450 50 0000 R CNN +F 1 "eSim_NPN" H 5300 2550 50 0000 R CNN +F 2 "" H 5550 2500 29 0000 C CNN +F 3 "" H 5350 2400 60 0000 C CNN + 1 5350 2400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 684ADF85 +P 6050 2400 +F 0 "Q5" H 5950 2450 50 0000 R CNN +F 1 "eSim_NPN" H 6000 2550 50 0000 R CNN +F 2 "" H 6250 2500 29 0000 C CNN +F 3 "" H 6050 2400 60 0000 C CNN + 1 6050 2400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 684AE05C +P 7100 2400 +F 0 "Q6" H 7000 2450 50 0000 R CNN +F 1 "eSim_NPN" H 7050 2550 50 0000 R CNN +F 2 "" H 7300 2500 29 0000 C CNN +F 3 "" H 7100 2400 60 0000 C CNN + 1 7100 2400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 684AE062 +P 7800 2400 +F 0 "Q9" H 7700 2450 50 0000 R CNN +F 1 "eSim_NPN" H 7750 2550 50 0000 R CNN +F 2 "" H 8000 2500 29 0000 C CNN +F 3 "" H 7800 2400 60 0000 C CNN + 1 7800 2400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 684AE0CE +P 5600 3050 +F 0 "Q3" H 5500 3100 50 0000 R CNN +F 1 "eSim_NPN" H 5550 3200 50 0000 R CNN +F 2 "" H 5800 3150 29 0000 C CNN +F 3 "" H 5600 3050 60 0000 C CNN + 1 5600 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 684AE0F9 +P 5600 3850 +F 0 "Q4" H 5500 3900 50 0000 R CNN +F 1 "eSim_NPN" H 5550 4000 50 0000 R CNN +F 2 "" H 5800 3950 29 0000 C CNN +F 3 "" H 5600 3850 60 0000 C CNN + 1 5600 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 684AE124 +P 7400 3050 +F 0 "Q7" H 7300 3100 50 0000 R CNN +F 1 "eSim_NPN" H 7350 3200 50 0000 R CNN +F 2 "" H 7600 3150 29 0000 C CNN +F 3 "" H 7400 3050 60 0000 C CNN + 1 7400 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 684AE15D +P 7400 3850 +F 0 "Q8" H 7300 3900 50 0000 R CNN +F 1 "eSim_NPN" H 7350 4000 50 0000 R CNN +F 2 "" H 7600 3950 29 0000 C CNN +F 3 "" H 7400 3850 60 0000 C CNN + 1 7400 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 684AE198 +P 4850 4050 +F 0 "Q1" H 4750 4100 50 0000 R CNN +F 1 "eSim_NPN" H 4800 4200 50 0000 R CNN +F 2 "" H 5050 4150 29 0000 C CNN +F 3 "" H 4850 4050 60 0000 C CNN + 1 4850 4050 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 684AE385 +P 5650 4400 +F 0 "R2" H 5700 4530 50 0000 C CNN +F 1 "500" H 5700 4350 50 0000 C CNN +F 2 "" H 5700 4380 30 0000 C CNN +F 3 "" V 5700 4450 30 0000 C CNN + 1 5650 4400 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 684AE3CA +P 4900 4400 +F 0 "R1" H 4950 4530 50 0000 C CNN +F 1 "500" H 4950 4350 50 0000 C CNN +F 2 "" H 4950 4380 30 0000 C CNN +F 3 "" V 4950 4450 30 0000 C CNN + 1 4900 4400 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 684AE411 +P 7450 4400 +F 0 "R3" H 7500 4530 50 0000 C CNN +F 1 "500" H 7500 4350 50 0000 C CNN +F 2 "" H 7500 4380 30 0000 C CNN +F 3 "" V 7500 4450 30 0000 C CNN + 1 7450 4400 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 684AE863 +P 4250 3400 +F 0 "U1" H 4300 3500 30 0000 C CNN +F 1 "PORT" H 4250 3400 30 0000 C CNN +F 2 "" H 4250 3400 60 0000 C CNN +F 3 "" H 4250 3400 60 0000 C CNN + 1 4250 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 684AEA59 +P 8400 3300 +F 0 "U1" H 8450 3400 30 0000 C CNN +F 1 "PORT" H 8400 3300 30 0000 C CNN +F 2 "" H 8400 3300 60 0000 C CNN +F 3 "" H 8400 3300 60 0000 C CNN + 2 8400 3300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 684AEA98 +P 8400 3550 +F 0 "U1" H 8450 3650 30 0000 C CNN +F 1 "PORT" H 8400 3550 30 0000 C CNN +F 2 "" H 8400 3550 60 0000 C CNN +F 3 "" H 8400 3550 60 0000 C CNN + 3 8400 3550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 684AEB4A +P 4250 3050 +F 0 "U1" H 4300 3150 30 0000 C CNN +F 1 "PORT" H 4250 3050 30 0000 C CNN +F 2 "" H 4250 3050 60 0000 C CNN +F 3 "" H 4250 3050 60 0000 C CNN + 4 4250 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 684AEC45 +P 3950 3850 +F 0 "U1" H 4000 3950 30 0000 C CNN +F 1 "PORT" H 3950 3850 30 0000 C CNN +F 2 "" H 3950 3850 60 0000 C CNN +F 3 "" H 3950 3850 60 0000 C CNN + 5 3950 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 684AECBB +P 5450 1350 +F 0 "U1" H 5500 1450 30 0000 C CNN +F 1 "PORT" H 5450 1350 30 0000 C CNN +F 2 "" H 5450 1350 60 0000 C CNN +F 3 "" H 5450 1350 60 0000 C CNN + 6 5450 1350 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 684AED24 +P 3000 1050 +F 0 "U1" H 3050 1150 30 0000 C CNN +F 1 "PORT" H 3000 1050 30 0000 C CNN +F 2 "" H 3000 1050 60 0000 C CNN +F 3 "" H 3000 1050 60 0000 C CNN + 7 3000 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 684AEDED +P 4250 2650 +F 0 "U1" H 4300 2750 30 0000 C CNN +F 1 "PORT" H 4250 2650 30 0000 C CNN +F 2 "" H 4250 2650 60 0000 C CNN +F 3 "" H 4250 2650 60 0000 C CNN + 8 4250 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 684AEE7E +P 3000 1350 +F 0 "U1" H 3050 1450 30 0000 C CNN +F 1 "PORT" H 3000 1350 30 0000 C CNN +F 2 "" H 3000 1350 60 0000 C CNN +F 3 "" H 3000 1350 60 0000 C CNN + 9 3000 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 684AEEC3 +P 4250 2450 +F 0 "U1" H 4300 2550 30 0000 C CNN +F 1 "PORT" H 4250 2450 30 0000 C CNN +F 2 "" H 4250 2450 60 0000 C CNN +F 3 "" H 4250 2450 60 0000 C CNN + 10 4250 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 684AEF8E +P 3000 1650 +F 0 "U1" H 3050 1750 30 0000 C CNN +F 1 "PORT" H 3000 1650 30 0000 C CNN +F 2 "" H 3000 1650 60 0000 C CNN +F 3 "" H 3000 1650 60 0000 C CNN + 11 3000 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 684AEFFD +P 7700 1100 +F 0 "U1" H 7750 1200 30 0000 C CNN +F 1 "PORT" H 7700 1100 30 0000 C CNN +F 2 "" H 7700 1100 60 0000 C CNN +F 3 "" H 7700 1100 60 0000 C CNN + 12 7700 1100 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 684AF0F2 +P 3000 1900 +F 0 "U1" H 3050 2000 30 0000 C CNN +F 1 "PORT" H 3000 1900 30 0000 C CNN +F 2 "" H 3000 1900 60 0000 C CNN +F 3 "" H 3000 1900 60 0000 C CNN + 13 3000 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 684AF1C4 +P 4350 4750 +F 0 "U1" H 4400 4850 30 0000 C CNN +F 1 "PORT" H 4350 4750 30 0000 C CNN +F 2 "" H 4350 4750 60 0000 C CNN +F 3 "" H 4350 4750 60 0000 C CNN + 14 4350 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5450 2600 5450 2750 +Wire Wire Line + 5450 2750 5950 2750 +Wire Wire Line + 5950 2750 5950 2600 +Wire Wire Line + 5700 2850 5700 2750 +Connection ~ 5700 2750 +Wire Wire Line + 7200 2600 7200 2750 +Wire Wire Line + 7200 2750 7700 2750 +Wire Wire Line + 7700 2750 7700 2600 +Wire Wire Line + 7500 2850 7500 2750 +Connection ~ 7500 2750 +Wire Wire Line + 5700 3250 5700 3650 +Wire Wire Line + 7500 3250 7500 3650 +Wire Wire Line + 6250 2400 6900 2400 +Wire Wire Line + 5450 1600 5450 2200 +Wire Wire Line + 5450 1900 7200 1900 +Wire Wire Line + 7700 1350 7700 2200 +Wire Wire Line + 5950 2200 5950 2000 +Wire Wire Line + 5950 2000 7700 2000 +Wire Wire Line + 5150 2400 5150 2650 +Wire Wire Line + 4500 2650 8000 2650 +Wire Wire Line + 8000 2650 8000 2400 +Wire Wire Line + 4200 3850 5400 3850 +Wire Wire Line + 4950 4300 4950 4250 +Wire Wire Line + 5700 4050 5700 4300 +Wire Wire Line + 7500 4050 7500 4300 +Wire Wire Line + 4950 4600 4950 4750 +Wire Wire Line + 4600 4750 7500 4750 +Wire Wire Line + 5700 4750 5700 4600 +Wire Wire Line + 7500 4750 7500 4600 +Connection ~ 5700 4750 +Wire Wire Line + 4650 4050 4300 4050 +Wire Wire Line + 4300 4050 4300 3850 +Connection ~ 4950 3850 +Connection ~ 4950 4750 +Connection ~ 4300 3850 +Wire Wire Line + 4500 3400 7200 3400 +Wire Wire Line + 7200 3400 7200 3050 +Wire Wire Line + 4500 3050 5400 3050 +Connection ~ 5150 2650 +Wire Wire Line + 4500 2450 4500 2200 +Wire Wire Line + 4500 2200 6600 2200 +Wire Wire Line + 6600 2200 6600 2400 +Connection ~ 6600 2400 +Connection ~ 5450 1900 +Wire Wire Line + 7500 3300 8150 3300 +Connection ~ 7500 3300 +Wire Wire Line + 8150 3550 5700 3550 +Connection ~ 5700 3550 +NoConn ~ 3250 1050 +NoConn ~ 3250 1350 +NoConn ~ 3250 1650 +NoConn ~ 3250 1900 +Wire Wire Line + 7200 3850 7200 4100 +Wire Wire Line + 7200 4100 5300 4100 +Wire Wire Line + 5300 4100 5300 3850 +Connection ~ 5300 3850 +Wire Wire Line + 7200 1900 7200 2200 +Connection ~ 7700 2000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1496/mc1496.sub b/library/SubcircuitLibrary/mc1496/mc1496.sub new file mode 100644 index 000000000..67de09f28 --- /dev/null +++ b/library/SubcircuitLibrary/mc1496/mc1496.sub @@ -0,0 +1,19 @@ +* Subcircuit mc1496 +.subckt mc1496 net-_q7-pad2_ net-_q7-pad3_ net-_q3-pad3_ net-_q3-pad2_ net-_q1-pad1_ net-_q2-pad1_ ? net-_q2-pad2_ ? net-_q5-pad2_ ? net-_q5-pad1_ ? net-_r1-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\mc1496\mc1496.cir +.include NPN.lib +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q5-pad2_ net-_q2-pad3_ Q2N2222 +q6 net-_q2-pad1_ net-_q5-pad2_ net-_q6-pad3_ Q2N2222 +q9 net-_q5-pad1_ net-_q2-pad2_ net-_q6-pad3_ Q2N2222 +q3 net-_q2-pad3_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q4 net-_q3-pad3_ net-_q1-pad1_ net-_q4-pad3_ Q2N2222 +q7 net-_q6-pad3_ net-_q7-pad2_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q1-pad1_ net-_q8-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2222 +r2 net-_q4-pad3_ net-_r1-pad2_ 500 +r1 net-_q1-pad3_ net-_r1-pad2_ 500 +r3 net-_q8-pad3_ net-_r1-pad2_ 500 +* Control Statements + +.ends mc1496 \ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1496/mc1496_Previous_Values.xml b/library/SubcircuitLibrary/mc1496/mc1496_Previous_Values.xml new file mode 100644 index 000000000..c5e4dddb9 --- /dev/null +++ b/library/SubcircuitLibrary/mc1496/mc1496_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.110msusms \ No newline at end of file diff --git a/library/SubcircuitLibrary/tc4008bp_ic/analysis b/library/SubcircuitLibrary/tc4008bp_ic/analysis new file mode 100644 index 000000000..edc4bc4f9 --- /dev/null +++ b/library/SubcircuitLibrary/tc4008bp_ic/analysis @@ -0,0 +1 @@ +.tran 200e-03 10e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic-cache.lib b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic-cache.lib new file mode 100644 index 000000000..e0605f3e5 --- /dev/null +++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic-cache.lib @@ -0,0 +1,150 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir new file mode 100644 index 000000000..400c40b0e --- /dev/null +++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir @@ -0,0 +1,55 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\tc4008bp_ic\tc4008bp_ic.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/09/25 23:55:17 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U7 Net-_U1-Pad1_ Net-_U1-Pad15_ Net-_U16-Pad1_ d_nor +U8 Net-_U1-Pad1_ Net-_U1-Pad15_ Net-_U11-Pad1_ d_nand +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U11-Pad2_ Net-_U16-Pad3_ d_nor +U20 Net-_U16-Pad3_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_xor +U30 Net-_U20-Pad3_ Net-_U1-Pad13_ d_inverter +U50 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U12-Pad1_ d_nor +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U14-Pad2_ d_nand +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U14 Net-_U12-Pad2_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nand +U23 Net-_U12-Pad2_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_and +U33 Net-_U21-Pad2_ Net-_U23-Pad3_ Net-_U20-Pad2_ d_nor +U21 Net-_U14-Pad2_ Net-_U21-Pad2_ d_inverter +U24 Net-_U14-Pad3_ Net-_U23-Pad2_ Net-_U24-Pad3_ d_xor +U34 Net-_U24-Pad3_ Net-_U1-Pad12_ d_inverter +U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U15-Pad1_ d_nor +U4 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U22-Pad1_ d_nand +U9 Net-_U22-Pad1_ Net-_U15-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor +U26 Net-_U15-Pad1_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_or +U27 Net-_U15-Pad3_ Net-_U26-Pad2_ Net-_U27-Pad3_ d_xor +U35 Net-_U22-Pad1_ Net-_U26-Pad3_ Net-_U23-Pad2_ d_nand +U36 Net-_U27-Pad3_ Net-_U1-Pad11_ d_inverter +U5 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U10-Pad1_ d_nor +U6 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U13-Pad2_ d_nand +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U13 Net-_U10-Pad2_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nand +U25 Net-_U10-Pad2_ Net-_U1-Pad9_ Net-_U25-Pad3_ d_and +U37 Net-_U29-Pad2_ Net-_U25-Pad3_ Net-_U26-Pad2_ d_nor +U29 Net-_U13-Pad2_ Net-_U29-Pad2_ d_inverter +U28 Net-_U13-Pad3_ Net-_U1-Pad9_ Net-_U28-Pad3_ d_xor +U38 Net-_U28-Pad3_ Net-_U1-Pad10_ d_inverter +U17 Net-_U15-Pad1_ Net-_U13-Pad2_ Net-_U17-Pad3_ d_or +U22 Net-_U22-Pad1_ Net-_U17-Pad3_ Net-_U22-Pad3_ d_and +U32 Net-_U12-Pad1_ Net-_U22-Pad3_ Net-_U32-Pad3_ d_or +U39 Net-_U14-Pad2_ Net-_U32-Pad3_ Net-_U39-Pad3_ d_and +U41 Net-_U16-Pad1_ Net-_U39-Pad3_ Net-_U41-Pad3_ d_or +U42 Net-_U11-Pad1_ Net-_U41-Pad3_ Net-_U42-Pad3_ d_nand +U43 Net-_U40-Pad3_ Net-_U42-Pad3_ Net-_U43-Pad3_ d_nor +U44 Net-_U43-Pad3_ Net-_U1-Pad14_ d_inverter +U19 Net-_U15-Pad1_ Net-_U10-Pad1_ Net-_U19-Pad3_ d_nor +U18 Net-_U16-Pad1_ Net-_U12-Pad1_ Net-_U18-Pad3_ d_nor +U31 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U31-Pad3_ d_nor +U40 Net-_U1-Pad9_ Net-_U31-Pad3_ Net-_U40-Pad3_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT + +.end diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir.out b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir.out new file mode 100644 index 000000000..9c3de971b --- /dev/null +++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir.out @@ -0,0 +1,188 @@ +* c:\fossee\esim\library\subcircuitlibrary\tc4008bp_ic\tc4008bp_ic.cir + +* u7 net-_u1-pad1_ net-_u1-pad15_ net-_u16-pad1_ d_nor +* u8 net-_u1-pad1_ net-_u1-pad15_ net-_u11-pad1_ d_nand +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u11-pad2_ net-_u16-pad3_ d_nor +* u20 net-_u16-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_xor +* u30 net-_u20-pad3_ net-_u1-pad13_ d_inverter +* u50 net-_u1-pad2_ net-_u1-pad3_ net-_u12-pad1_ d_nor +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u14-pad2_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u14 net-_u12-pad2_ net-_u14-pad2_ net-_u14-pad3_ d_nand +* u23 net-_u12-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and +* u33 net-_u21-pad2_ net-_u23-pad3_ net-_u20-pad2_ d_nor +* u21 net-_u14-pad2_ net-_u21-pad2_ d_inverter +* u24 net-_u14-pad3_ net-_u23-pad2_ net-_u24-pad3_ d_xor +* u34 net-_u24-pad3_ net-_u1-pad12_ d_inverter +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u15-pad1_ d_nor +* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u22-pad1_ d_nand +* u9 net-_u22-pad1_ net-_u15-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u26 net-_u15-pad1_ net-_u26-pad2_ net-_u26-pad3_ d_or +* u27 net-_u15-pad3_ net-_u26-pad2_ net-_u27-pad3_ d_xor +* u35 net-_u22-pad1_ net-_u26-pad3_ net-_u23-pad2_ d_nand +* u36 net-_u27-pad3_ net-_u1-pad11_ d_inverter +* u5 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad1_ d_nor +* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u13-pad2_ d_nand +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u13 net-_u10-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_nand +* u25 net-_u10-pad2_ net-_u1-pad9_ net-_u25-pad3_ d_and +* u37 net-_u29-pad2_ net-_u25-pad3_ net-_u26-pad2_ d_nor +* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter +* u28 net-_u13-pad3_ net-_u1-pad9_ net-_u28-pad3_ d_xor +* u38 net-_u28-pad3_ net-_u1-pad10_ d_inverter +* u17 net-_u15-pad1_ net-_u13-pad2_ net-_u17-pad3_ d_or +* u22 net-_u22-pad1_ net-_u17-pad3_ net-_u22-pad3_ d_and +* u32 net-_u12-pad1_ net-_u22-pad3_ net-_u32-pad3_ d_or +* u39 net-_u14-pad2_ net-_u32-pad3_ net-_u39-pad3_ d_and +* u41 net-_u16-pad1_ net-_u39-pad3_ net-_u41-pad3_ d_or +* u42 net-_u11-pad1_ net-_u41-pad3_ net-_u42-pad3_ d_nand +* u43 net-_u40-pad3_ net-_u42-pad3_ net-_u43-pad3_ d_nor +* u44 net-_u43-pad3_ net-_u1-pad14_ d_inverter +* u19 net-_u15-pad1_ net-_u10-pad1_ net-_u19-pad3_ d_nor +* u18 net-_u16-pad1_ net-_u12-pad1_ net-_u18-pad3_ d_nor +* u31 net-_u18-pad3_ net-_u19-pad3_ net-_u31-pad3_ d_nor +* u40 net-_u1-pad9_ net-_u31-pad3_ net-_u40-pad3_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port +a1 [net-_u1-pad1_ net-_u1-pad15_ ] net-_u16-pad1_ u7 +a2 [net-_u1-pad1_ net-_u1-pad15_ ] net-_u11-pad1_ u8 +a3 net-_u11-pad1_ net-_u11-pad2_ u11 +a4 [net-_u16-pad1_ net-_u11-pad2_ ] net-_u16-pad3_ u16 +a5 [net-_u16-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a6 net-_u20-pad3_ net-_u1-pad13_ u30 +a7 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u12-pad1_ u50 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u14-pad2_ u2 +a9 net-_u12-pad1_ net-_u12-pad2_ u12 +a10 [net-_u12-pad2_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a11 [net-_u12-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a12 [net-_u21-pad2_ net-_u23-pad3_ ] net-_u20-pad2_ u33 +a13 net-_u14-pad2_ net-_u21-pad2_ u21 +a14 [net-_u14-pad3_ net-_u23-pad2_ ] net-_u24-pad3_ u24 +a15 net-_u24-pad3_ net-_u1-pad12_ u34 +a16 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u15-pad1_ u3 +a17 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u22-pad1_ u4 +a18 net-_u22-pad1_ net-_u15-pad2_ u9 +a19 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a20 [net-_u15-pad1_ net-_u26-pad2_ ] net-_u26-pad3_ u26 +a21 [net-_u15-pad3_ net-_u26-pad2_ ] net-_u27-pad3_ u27 +a22 [net-_u22-pad1_ net-_u26-pad3_ ] net-_u23-pad2_ u35 +a23 net-_u27-pad3_ net-_u1-pad11_ u36 +a24 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad1_ u5 +a25 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u13-pad2_ u6 +a26 net-_u10-pad1_ net-_u10-pad2_ u10 +a27 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a28 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u25-pad3_ u25 +a29 [net-_u29-pad2_ net-_u25-pad3_ ] net-_u26-pad2_ u37 +a30 net-_u13-pad2_ net-_u29-pad2_ u29 +a31 [net-_u13-pad3_ net-_u1-pad9_ ] net-_u28-pad3_ u28 +a32 net-_u28-pad3_ net-_u1-pad10_ u38 +a33 [net-_u15-pad1_ net-_u13-pad2_ ] net-_u17-pad3_ u17 +a34 [net-_u22-pad1_ net-_u17-pad3_ ] net-_u22-pad3_ u22 +a35 [net-_u12-pad1_ net-_u22-pad3_ ] net-_u32-pad3_ u32 +a36 [net-_u14-pad2_ net-_u32-pad3_ ] net-_u39-pad3_ u39 +a37 [net-_u16-pad1_ net-_u39-pad3_ ] net-_u41-pad3_ u41 +a38 [net-_u11-pad1_ net-_u41-pad3_ ] net-_u42-pad3_ u42 +a39 [net-_u40-pad3_ net-_u42-pad3_ ] net-_u43-pad3_ u43 +a40 net-_u43-pad3_ net-_u1-pad14_ u44 +a41 [net-_u15-pad1_ net-_u10-pad1_ ] net-_u19-pad3_ u19 +a42 [net-_u16-pad1_ net-_u12-pad1_ ] net-_u18-pad3_ u18 +a43 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u31-pad3_ u31 +a44 [net-_u1-pad9_ net-_u31-pad3_ ] net-_u40-pad3_ u40 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u24 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u27 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u28 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 200e-03 10e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.pro b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sch b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sch new file mode 100644 index 000000000..d784c7685 --- /dev/null +++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sch @@ -0,0 +1,1019 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nor U7 +U 1 1 686EAFDD +P 10550 6050 +F 0 "U7" H 10550 6050 60 0000 C CNN +F 1 "d_nor" H 10600 6150 60 0000 C CNN +F 2 "" H 10550 6050 60 0000 C CNN +F 3 "" H 10550 6050 60 0000 C CNN + 1 10550 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 686EAFDE +P 10550 6550 +F 0 "U8" H 10550 6550 60 0000 C CNN +F 1 "d_nand" H 10600 6650 60 0000 C CNN +F 2 "" H 10550 6550 60 0000 C CNN +F 3 "" H 10550 6550 60 0000 C CNN + 1 10550 6550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 686EAFDF +P 11750 6500 +F 0 "U11" H 11750 6400 60 0000 C CNN +F 1 "d_inverter" H 11750 6650 60 0000 C CNN +F 2 "" H 11800 6450 60 0000 C CNN +F 3 "" H 11800 6450 60 0000 C CNN + 1 11750 6500 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U16 +U 1 1 686EAFE0 +P 12950 6250 +F 0 "U16" H 12950 6250 60 0000 C CNN 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C CNN +F 1 "PORT" H 7600 8200 30 0000 C CNN +F 2 "" H 7600 8200 60 0000 C CNN +F 3 "" H 7600 8200 60 0000 C CNN + 4 7600 8200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 686EF117 +P 8100 9150 +F 0 "U1" H 8150 9250 30 0000 C CNN +F 1 "PORT" H 8100 9150 30 0000 C CNN +F 2 "" H 8100 9150 60 0000 C CNN +F 3 "" H 8100 9150 60 0000 C CNN + 5 8100 9150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 686EF32C +P 7950 9900 +F 0 "U1" H 8000 10000 30 0000 C CNN +F 1 "PORT" H 7950 9900 30 0000 C CNN +F 2 "" H 7950 9900 60 0000 C CNN +F 3 "" H 7950 9900 60 0000 C CNN + 6 7950 9900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 686EF63B +P 7850 10600 +F 0 "U1" H 7900 10700 30 0000 C CNN +F 1 "PORT" H 7850 10600 30 0000 C CNN +F 2 "" H 7850 10600 60 0000 C CNN +F 3 "" H 7850 10600 60 0000 C CNN + 7 7850 10600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 686EF78C +P 7700 11200 +F 0 "U1" H 7750 11300 30 0000 C CNN +F 1 "PORT" H 7700 11200 30 0000 C CNN +F 2 "" H 7700 11200 60 0000 C CNN +F 3 "" H 7700 11200 60 0000 C CNN + 9 7700 11200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 686EFC2D +P 17400 10550 +F 0 "U1" H 17450 10650 30 0000 C CNN +F 1 "PORT" H 17400 10550 30 0000 C CNN +F 2 "" H 17400 10550 60 0000 C CNN +F 3 "" H 17400 10550 60 0000 C CNN + 10 17400 10550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 686EFE88 +P 17000 9150 +F 0 "U1" H 17050 9250 30 0000 C CNN +F 1 "PORT" H 17000 9150 30 0000 C CNN +F 2 "" H 17000 9150 60 0000 C CNN +F 3 "" H 17000 9150 60 0000 C CNN + 11 17000 9150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 686EFF3D +P 20050 7150 +F 0 "U1" H 20100 7250 30 0000 C CNN +F 1 "PORT" H 20050 7150 30 0000 C CNN +F 2 "" H 20050 7150 60 0000 C CNN +F 3 "" H 20050 7150 60 0000 C CNN + 12 20050 7150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 686F0059 +P 19200 6250 +F 0 "U1" H 19250 6350 30 0000 C CNN +F 1 "PORT" H 19200 6250 30 0000 C CNN +F 2 "" H 19200 6250 60 0000 C CNN +F 3 "" H 19200 6250 60 0000 C CNN + 13 19200 6250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 686F03B2 +P 21750 2750 +F 0 "U1" H 21800 2850 30 0000 C CNN +F 1 "PORT" H 21750 2750 30 0000 C CNN +F 2 "" H 21750 2750 60 0000 C CNN +F 3 "" H 21750 2750 60 0000 C CNN + 14 21750 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 686F071A +P 7750 6550 +F 0 "U1" H 7800 6650 30 0000 C CNN +F 1 "PORT" H 7750 6550 30 0000 C CNN +F 2 "" H 7750 6550 60 0000 C CNN +F 3 "" H 7750 6550 60 0000 C CNN + 15 7750 6550 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sub b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sub new file mode 100644 index 000000000..7f584f9c3 --- /dev/null +++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sub @@ -0,0 +1,182 @@ +* Subcircuit tc4008bp_ic +.subckt tc4008bp_ic net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ +* c:\fossee\esim\library\subcircuitlibrary\tc4008bp_ic\tc4008bp_ic.cir +* u7 net-_u1-pad1_ net-_u1-pad15_ net-_u16-pad1_ d_nor +* u8 net-_u1-pad1_ net-_u1-pad15_ net-_u11-pad1_ d_nand +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u11-pad2_ net-_u16-pad3_ d_nor +* u20 net-_u16-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_xor +* u30 net-_u20-pad3_ net-_u1-pad13_ d_inverter +* u50 net-_u1-pad2_ net-_u1-pad3_ net-_u12-pad1_ d_nor +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u14-pad2_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u14 net-_u12-pad2_ net-_u14-pad2_ net-_u14-pad3_ d_nand +* u23 net-_u12-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and +* u33 net-_u21-pad2_ net-_u23-pad3_ net-_u20-pad2_ d_nor +* u21 net-_u14-pad2_ net-_u21-pad2_ d_inverter +* u24 net-_u14-pad3_ net-_u23-pad2_ net-_u24-pad3_ d_xor +* u34 net-_u24-pad3_ net-_u1-pad12_ d_inverter +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u15-pad1_ d_nor +* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u22-pad1_ d_nand +* u9 net-_u22-pad1_ net-_u15-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u26 net-_u15-pad1_ net-_u26-pad2_ net-_u26-pad3_ d_or +* u27 net-_u15-pad3_ net-_u26-pad2_ net-_u27-pad3_ d_xor +* u35 net-_u22-pad1_ net-_u26-pad3_ net-_u23-pad2_ d_nand +* u36 net-_u27-pad3_ net-_u1-pad11_ d_inverter +* u5 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad1_ d_nor +* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u13-pad2_ d_nand +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u13 net-_u10-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_nand +* u25 net-_u10-pad2_ net-_u1-pad9_ net-_u25-pad3_ d_and +* u37 net-_u29-pad2_ net-_u25-pad3_ net-_u26-pad2_ d_nor +* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter +* u28 net-_u13-pad3_ net-_u1-pad9_ net-_u28-pad3_ d_xor +* u38 net-_u28-pad3_ net-_u1-pad10_ d_inverter +* u17 net-_u15-pad1_ net-_u13-pad2_ net-_u17-pad3_ d_or +* u22 net-_u22-pad1_ net-_u17-pad3_ net-_u22-pad3_ d_and +* u32 net-_u12-pad1_ net-_u22-pad3_ net-_u32-pad3_ d_or +* u39 net-_u14-pad2_ net-_u32-pad3_ net-_u39-pad3_ d_and +* u41 net-_u16-pad1_ net-_u39-pad3_ net-_u41-pad3_ d_or +* u42 net-_u11-pad1_ net-_u41-pad3_ net-_u42-pad3_ d_nand +* u43 net-_u40-pad3_ net-_u42-pad3_ net-_u43-pad3_ d_nor +* u44 net-_u43-pad3_ net-_u1-pad14_ d_inverter +* u19 net-_u15-pad1_ net-_u10-pad1_ net-_u19-pad3_ d_nor +* u18 net-_u16-pad1_ net-_u12-pad1_ net-_u18-pad3_ d_nor +* u31 net-_u18-pad3_ net-_u19-pad3_ net-_u31-pad3_ d_nor +* u40 net-_u1-pad9_ net-_u31-pad3_ net-_u40-pad3_ d_and +a1 [net-_u1-pad1_ net-_u1-pad15_ ] net-_u16-pad1_ u7 +a2 [net-_u1-pad1_ net-_u1-pad15_ ] net-_u11-pad1_ u8 +a3 net-_u11-pad1_ net-_u11-pad2_ u11 +a4 [net-_u16-pad1_ net-_u11-pad2_ ] net-_u16-pad3_ u16 +a5 [net-_u16-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a6 net-_u20-pad3_ net-_u1-pad13_ u30 +a7 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u12-pad1_ u50 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u14-pad2_ u2 +a9 net-_u12-pad1_ net-_u12-pad2_ u12 +a10 [net-_u12-pad2_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a11 [net-_u12-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a12 [net-_u21-pad2_ net-_u23-pad3_ ] net-_u20-pad2_ u33 +a13 net-_u14-pad2_ net-_u21-pad2_ u21 +a14 [net-_u14-pad3_ net-_u23-pad2_ ] net-_u24-pad3_ u24 +a15 net-_u24-pad3_ net-_u1-pad12_ u34 +a16 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u15-pad1_ u3 +a17 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u22-pad1_ u4 +a18 net-_u22-pad1_ net-_u15-pad2_ u9 +a19 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a20 [net-_u15-pad1_ net-_u26-pad2_ ] net-_u26-pad3_ u26 +a21 [net-_u15-pad3_ net-_u26-pad2_ ] net-_u27-pad3_ u27 +a22 [net-_u22-pad1_ net-_u26-pad3_ ] net-_u23-pad2_ u35 +a23 net-_u27-pad3_ net-_u1-pad11_ u36 +a24 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad1_ u5 +a25 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u13-pad2_ u6 +a26 net-_u10-pad1_ net-_u10-pad2_ u10 +a27 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a28 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u25-pad3_ u25 +a29 [net-_u29-pad2_ net-_u25-pad3_ ] net-_u26-pad2_ u37 +a30 net-_u13-pad2_ net-_u29-pad2_ u29 +a31 [net-_u13-pad3_ net-_u1-pad9_ ] net-_u28-pad3_ u28 +a32 net-_u28-pad3_ net-_u1-pad10_ u38 +a33 [net-_u15-pad1_ net-_u13-pad2_ ] net-_u17-pad3_ u17 +a34 [net-_u22-pad1_ net-_u17-pad3_ ] net-_u22-pad3_ u22 +a35 [net-_u12-pad1_ net-_u22-pad3_ ] net-_u32-pad3_ u32 +a36 [net-_u14-pad2_ net-_u32-pad3_ ] net-_u39-pad3_ u39 +a37 [net-_u16-pad1_ net-_u39-pad3_ ] net-_u41-pad3_ u41 +a38 [net-_u11-pad1_ net-_u41-pad3_ ] net-_u42-pad3_ u42 +a39 [net-_u40-pad3_ net-_u42-pad3_ ] net-_u43-pad3_ u43 +a40 net-_u43-pad3_ net-_u1-pad14_ u44 +a41 [net-_u15-pad1_ net-_u10-pad1_ ] net-_u19-pad3_ u19 +a42 [net-_u16-pad1_ net-_u12-pad1_ ] net-_u18-pad3_ u18 +a43 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u31-pad3_ u31 +a44 [net-_u1-pad9_ net-_u31-pad3_ ] net-_u40-pad3_ u40 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u24 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u27 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u28 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends tc4008bp_ic \ No newline at end of file diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic_Previous_Values.xml b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic_Previous_Values.xml new file mode 100644 index 000000000..f7d1db7a0 --- /dev/null +++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes020010secmssecd_nord_nandd_inverterd_nord_xord_inverterd_nord_nandd_inverterd_nandd_andd_nord_inverterd_xord_inverterd_nord_nandd_inverterd_nord_ord_xord_nandd_inverterd_nord_nandd_inverterd_nandd_andd_nord_inverterd_xord_inverterd_ord_andd_ord_andd_ord_nandd_nord_inverterd_nord_nord_nord_and \ No newline at end of file