diff --git a/configs/config.msi_ms7e56 b/configs/config.msi_ms7e56 index 7604cf5ce66..e478f9882cd 100644 --- a/configs/config.msi_ms7e56 +++ b/configs/config.msi_ms7e56 @@ -1,3 +1,4 @@ +CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VGA_BIOS=y @@ -10,21 +11,24 @@ CONFIG_VGA_BIOS_FILE="Phoenix_generic_vbios.bin" CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_BOARD_MSI_PRO_B850_P=y +CONFIG_TPM_MEASURED_BOOT=y CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION=y CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE=y -# CONFIG_ON_DEVICE_ROM_LOAD is not set -CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y -CONFIG_YABEL_DIRECTHW=y +CONFIG_NO_GFX_INIT=y CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_TPM2=y +# CONFIG_TPM_HASH_SHA1 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_TAG_OR_REV="origin/cbmem_pci_rb_info" -CONFIG_EDK2_DEBUG=y +CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_LOAD_OPTION_ROMS=y # CONFIG_EDK2_PS2_SUPPORT is not set -CONFIG_EDK2_CUSTOM_BUILD_PARAMS="--pcd gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask=0x07" +CONFIG_EDK2_SERIAL_SUPPORT=y CONFIG_EDK2_ENABLE_IPXE=y CONFIG_IPXE_STABLE=y CONFIG_IPXE_ADD_SCRIPT=y @@ -43,11 +47,11 @@ CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y CONFIG_EDK2_DASHARO_POWER_CONFIG=y CONFIG_EDK2_DASHARO_PCI_CONFIG=y -CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y CONFIG_EDK2_BOOT_MENU_KEY=0x0015 CONFIG_EDK2_SETUP_MENU_KEY=0x0008 CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI=y CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y # CONFIG_EDK2_GRAPHICAL_CAPSULE_PROGRESS is not set @@ -55,5 +59,4 @@ CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y CONFIG_DISPLAY_MTRRS=y CONFIG_OPENSIL_DEBUG_PREFIX=y CONFIG_OPENSIL_DEBUG_APOB=y -# CONFIG_OPENSIL_DEBUG_FCH is not set # CONFIG_OPENSIL_DEBUG_XUSL_CMN is not set diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index fc8c11d4122..d4272a392d5 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -299,8 +299,11 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI) CONFIG_EDK2_DASHARO_IBECC_OPTION=$(CONFIG_EDK2_DASHARO_IBECC_OPTION) \ CONFIG_EDK2_DASHARO_SPD_PROFILE_OPTION=$(CONFIG_EDK2_DASHARO_SPD_PROFILE_OPTION) \ CONFIG_EDK2_CAPSULE_ON_DISK_SUPPORT=$(CONFIG_EDK2_CAPSULE_ON_DISK_SUPPORT) \ - CONFIG_EDK2_SHOW_CAPSULE_REPORT=$(CONFIG_EDK2_SHOW_CAPSULE_REPORT) - + CONFIG_EDK2_SHOW_CAPSULE_REPORT=$(CONFIG_EDK2_SHOW_CAPSULE_REPORT) \ + CONFIG_EDK2_AMD_GOP_DRIVER=$(CONFIG_EDK2_AMD_GOP_DRIVER) \ + CONFIG_EDK2_VGA_BIOS_VENDOR_ID=0x$(word 1,$(subst $(comma),$(spc),$(call strip_quotes,$(CONFIG_VGA_BIOS_ID)))) \ + CONFIG_EDK2_VGA_BIOS_DEVICE_ID=0x$(word 2,$(subst $(comma),$(spc),$(call strip_quotes,$(CONFIG_VGA_BIOS_ID)))) \ + CONFIG_VGA_BIOS_FILE=$(CONFIG_VGA_BIOS_FILE) $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG) $(MAKE) -C payloads/external/edk2 UniversalPayload \ diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index 870e2ad66e1..e3c4c654371 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -291,9 +291,17 @@ config EDK2_GOP_DRIVER help Select this option to have edk2 use an external GOP driver for display init. +config EDK2_AMD_GOP_DRIVER + bool "Add an AMD GOP driver to the Tianocore build" + depends on VGA_BIOS && NO_GFX_INIT && !EDK2_REPO_OFFICIAL && !EDK2_DISABLE_OPTION_ROMS + default y if VGA_BIOS && NO_GFX_INIT && EDK2_REPO_MRCHROMEBOX + help + Select this option to have edk2 use an external GOP driver for AMD display init. + config EDK2_GOP_FILE string "GOP driver file" - depends on EDK2_GOP_DRIVER + depends on EDK2_GOP_DRIVER || EDK2_AMD_GOP_DRIVER + default "AmdGopDriver.efi" if EDK2_AMD_GOP_DRIVER default "IntelGopDriver.efi" help The name of the GOP driver file passed to edk2. diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 3219160cccc..8f8c66738fb 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -456,7 +456,12 @@ endif ifneq ($(CONFIG_EDK2_FUM_AUTO_IPXE_BOOT),y) BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdFumAutoIpxeBoot=FALSE endif - +# USE_AMD_PLATFORM_GOP = FALSE +ifeq ($(CONFIG_EDK2_AMD_GOP_DRIVER),y) +BUILD_STR += -D USE_AMD_PLATFORM_GOP=TRUE +BUILD_STR += --pcd gDasharoPayloadPkgTokenSpaceGuid.AmdVbiosOptionRomVendorId=$(CONFIG_EDK2_VGA_BIOS_VENDOR_ID) +BUILD_STR += --pcd gDasharoPayloadPkgTokenSpaceGuid.AmdVbiosOptionRomDeviceId=$(CONFIG_EDK2_VGA_BIOS_DEVICE_ID) +endif endif # !CONFIG_EDK2_REPO_OFFICIAL # @@ -549,6 +554,11 @@ gop_driver: $(EDK2_PATH) cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/IntelGopDriver.efi; \ cp $(top)/$(CONFIG_INTEL_GMA_VBT_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/vbt.bin; \ fi; \ + if [ -n "$(CONFIG_EDK2_AMD_GOP_DRIVER)" ]; then \ + echo "Using GOP driver $(CONFIG_EDK2_GOP_FILE)"; \ + cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/AmdGopDriver.efi; \ + cp $(top)/$(CONFIG_VGA_BIOS_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/Vbios.bin; \ + fi; \ lan_rom: $(EDK2_PATH) case "$(CONFIG_EDK2_LAN_ROM_DRIVER)" in \ diff --git a/src/mainboard/msi/ms7e56/data.apcb b/src/mainboard/msi/ms7e56/data.apcb index 3147362a84e..8712aced369 100644 Binary files a/src/mainboard/msi/ms7e56/data.apcb and b/src/mainboard/msi/ms7e56/data.apcb differ diff --git a/src/mainboard/msi/ms7e56/data_rec.apcb b/src/mainboard/msi/ms7e56/data_rec.apcb index 30dd75fc128..2e4d805dd08 100644 Binary files a/src/mainboard/msi/ms7e56/data_rec.apcb and b/src/mainboard/msi/ms7e56/data_rec.apcb differ diff --git a/src/mainboard/msi/ms7e56/data_rec68.apcb b/src/mainboard/msi/ms7e56/data_rec68.apcb index 3147362a84e..7a2af0293ed 100644 Binary files a/src/mainboard/msi/ms7e56/data_rec68.apcb and b/src/mainboard/msi/ms7e56/data_rec68.apcb differ diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index 586b69f44e1..f211c5ced4b 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -233,7 +233,15 @@ chip soc/amd/phoenix end device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A - device ref gfx on end # Internal GPU (GFX) + device ref gfx on + chip drivers/amd/opensil/mpio + register "type" = "IFTYPE_DDI" + register "ddi_connector" = "ConnHDMI" + register "aux" = "DdiAux1" + register "hdp" = "DdiHdp1" + device generic 0 on end + end + end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) device ref crypto on end # Crypto Coprocessor device ref xhci_0 on diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 024afbe7e5f..bb37c9ae1eb 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -36,6 +36,10 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; * | (VERSTAGE_SIZE) | * +--------------------------------+ VERSTAGE_ADDR * | | + * | Promontory FW (if reqd) | + * | (256K) | + * +--------------------------------+ PROMONTORY_FW_ADDR + * | | * | FSP-M | * | (FSP_M_SIZE) | * +--------------------------------+ FSP_M_ADDR @@ -102,6 +106,10 @@ SECTIONS REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) #endif +#if CONFIG_PROMONTORY_FW_ADDR > 0 + REGION(promontory, CONFIG_PROMONTORY_FW_ADDR, 256K, 4K) +#endif + #if CONFIG(VBOOT_SEPARATE_VERSTAGE) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index 9f1c1e8cbd5..fe05d9c4d5f 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -47,7 +47,7 @@ struct embedded_firmware { uint32_t reserved_2Ch; uint32_t promontory_fw_ptr; uint32_t lp_promontory_fw_ptr; - uint32_t reserved_38h; + uint32_t promontory19_fw_ptr; uint32_t reserved_3Ch; uint8_t spi_readmode_f15_mod_60_6f; uint8_t fast_speed_new_f15_mod_60_6f; @@ -65,5 +65,6 @@ struct embedded_firmware { } __packed __aligned(16); bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed); +size_t efs_read_promontory_fw(void *buf); #endif /* AMD_COMMON_PSP_EFS_H */ diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk index 9e12743190a..c8dbb0965ab 100644 --- a/src/soc/amd/common/block/psp/Makefile.mk +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -10,6 +10,7 @@ smm-y += psp_smm.c bootblock-y += psp_efs.c verstage-y += psp_efs.c +ramstage-y += psp_efs.c all-y += ftpm.c diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c index fa69aea5548..a22c17dcadf 100644 --- a/src/soc/amd/common/block/psp/psp_efs.c +++ b/src/soc/amd/common/block/psp/psp_efs.c @@ -3,9 +3,13 @@ #include #include #include +#include #include +#include #include +#define PSP_FW_FILE_HEADER_SIZE 256 + bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed) { bool ret = false; @@ -28,3 +32,62 @@ bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed) rdev_munmap(boot_device_ro(), efs); return ret; } + +size_t efs_read_promontory_fw(void *buf) +{ + struct embedded_firmware *efs; + const struct region_device *boot_dev = boot_device_ro(); + uint8_t file_header[PSP_FW_FILE_HEADER_SIZE + 8]; + size_t read_bytes, fw_size; + uint32_t offset; + + if (!boot_dev || !buf) + return 0; + + efs = rdev_mmap(boot_dev, EFS_OFFSET, sizeof(*efs)); + if (!efs) + return 0; + + if (efs->signature != EMBEDDED_FW_SIGNATURE) { + rdev_munmap(boot_dev, efs); + return 0; + } + + offset = efs->promontory_fw_ptr; + rdev_munmap(boot_dev, efs); + + read_bytes = rdev_readat(boot_dev, file_header, offset, sizeof(file_header)); + if (read_bytes != sizeof(file_header)) + return 0; + + /* Get Promontory FW size */ + if (strncmp((char *)&file_header[0x10], "$PS1", 4)) { + /* Check Promontory FW signature */ + if (!strncmp((char *)file_header, "_PT_", 4)) + fw_size = *(uint32_t *)&file_header[4]; + else + return 0; + } else { + /* Check Promontory FW signature */ + if (!strncmp((char *)&file_header[PSP_FW_FILE_HEADER_SIZE], "_PT_", 4)) + fw_size = *(uint32_t *)&file_header[PSP_FW_FILE_HEADER_SIZE + 4]; + else + return 0; + + offset += PSP_FW_FILE_HEADER_SIZE; + } + + if (fw_size > 256 * KiB) { + printk(BIOS_DEBUG, "Found Promontory FW too big (size: %lx)\n", fw_size); + return 0; + } + + printk(BIOS_DEBUG, "Found Promontory FW @ 0x%08x (size: %lx)\n", + offset, fw_size); + + read_bytes = rdev_readat(boot_dev, buf, offset, fw_size); + if (read_bytes != fw_size) + return 0; + + return fw_size; +} diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 6f82513e3be..fc5ba462590 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -228,6 +228,15 @@ config VERSTAGE_ADDR Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86. +config PROMONTORY_FW_ADDR + hex + default 0x21A0000 if SOC_AMD_PHOENIX_AM5 + default 0x0 + help + Sets the address in DRAM where Promontory FW should be loaded on AM5. + Promontory needs ~160KB of space. We allocate 256KB between romstage + and verstage, so that it will be placed in early reserved DRAM. + config VERSTAGE_SIZE hex depends on VBOOT_SEPARATE_VERSTAGE diff --git a/src/vendorcode/amd/opensil/Kconfig.debug b/src/vendorcode/amd/opensil/Kconfig.debug index 3066844e56f..c57574c20b3 100644 --- a/src/vendorcode/amd/opensil/Kconfig.debug +++ b/src/vendorcode/amd/opensil/Kconfig.debug @@ -96,6 +96,12 @@ config OPENSIL_DEBUG_GFX help Enable printing graphics related messages. +config OPENSIL_DEBUG_PROM + bool "Enable Promontory messages" + default y + help + Enable printing Promontory related messages. + config OPENSIL_DEBUG_XUSL_CMN bool "Enable xUSL CommonLib messages" default y diff --git a/src/vendorcode/amd/opensil/phoenix_poc/filter.h b/src/vendorcode/amd/opensil/phoenix_poc/filter.h index 9852a7c2642..533884e8add 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/filter.h +++ b/src/vendorcode/amd/opensil/phoenix_poc/filter.h @@ -13,6 +13,7 @@ #define DEBUG_FILTER_CXL 0x00000200UL #define DEBUG_FILTER_RCMGR 0x00000800UL #define DEBUG_FILTER_GFX 0x00001000UL +#define DEBUG_FILTER_PROM 0x00002000UL #define SIL_DEBUG(topic) (CONFIG(OPENSIL_DEBUG_##topic) ? DEBUG_FILTER_##topic : 0) @@ -28,4 +29,5 @@ SIL_DEBUG(RAS) | \ SIL_DEBUG(CXL) | \ SIL_DEBUG(RCMGR) | \ - SIL_DEBUG(GFX)) + SIL_DEBUG(GFX) | \ + SIL_DEBUG(PROM)) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c index ee678539400..5dd5eae7f0b 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -12,6 +13,8 @@ #include "chip.h" +MPIO_DDI_DESCRIPTOR ddi_descriptor_list[MAX_DDI_PORTS]; + static void mpio_params_config(SIL_CONTEXT *SilContext) { MPIOCLASS_COMMON_INPUT_BLK *mpio_data = SilFindStructure(SilContext, SilId_MpioClass, 0); @@ -86,6 +89,8 @@ static void mpio_params_config(SIL_CONTEXT *SilContext) /* TODO handle this differently on multisocket */ mpio_data->PcieTopologyData.PlatformData[0].Flags = DESCRIPTOR_TERMINATE_LIST; mpio_data->PcieTopologyData.PlatformData[0].PciePortList = mpio_data->PcieTopologyData.PortList; + ddi_descriptor_list[0].Flags = DESCRIPTOR_TERMINATE_LIST; + mpio_data->PcieTopologyData.PlatformData[0].DdiLinkList = ddi_descriptor_list; } WEAK_DEV_PTR(usb4_router_0); @@ -96,6 +101,7 @@ WEAK_DEV_PTR(usb4_pcie_bridge_1); static void nbio_params_config(SIL_CONTEXT *SilContext) { NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilContext, SilId_NbioClass, 0); + GFXCLASS_INPUT_BLK *gfx_data = SilFindStructure(SilContext, SilId_GfxClass, 0); NBIO_CONFIG_DATA *input = &nbio_data->NbioConfigData; input->EsmEnableAllRootPorts = false; input->EsmTargetSpeed = 16; @@ -105,35 +111,47 @@ static void nbio_params_config(SIL_CONTEXT *SilContext) input->Usb4Rt0PcieTnlEn = is_dev_enabled(DEV_PTR(usb4_pcie_bridge_0)); input->Usb4Rt1En = is_dev_enabled(DEV_PTR(usb4_router_1)); input->Usb4Rt1PcieTnlEn = is_dev_enabled(DEV_PTR(usb4_pcie_bridge_1)); + gfx_data->Usb4Rt0En = input->Usb4Rt0En; + gfx_data->Usb4Rt1En = input->Usb4Rt1En; } #ifndef MPIO_ENGINE_DATA_INITIALIZER -#define MPIO_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane, mHotplug, mGpioGroupId) \ - { .EngineType = mType, \ - .HotPluggable = mHotplug, \ - .StartLane = mStartLane, \ - .EndLane = mEndLane, \ - .GpioGroupId = mGpioGroupId, \ - } +#define MPIO_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane, mHotplug, mGpioGroupId) \ + { \ + .EngineType = mType, \ + .HotPluggable = mHotplug, \ + .StartLane = mStartLane, \ + .EndLane = mEndLane, \ + .GpioGroupId = mGpioGroupId, \ + } #endif #ifndef MPIO_PORT_DATA_INITIALIZER_PCIE -#define MPIO_PORT_DATA_INITIALIZER_PCIE(mPortPresent, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, \ - mMaxLinkCap, mAspm, mAspmL1_1, mAspmL1_2, mClkPmSupport) \ - { \ - .PortPresent = mPortPresent, \ - .DeviceNumber = mDevAddress, \ - .FunctionNumber = mDevFunction, \ - .LinkSpeedCapability = mMaxLinkSpeed, \ - .LinkAspm = mAspm, \ - .LinkAspmL1_1 = mAspmL1_1, \ - .LinkAspmL1_2 = mAspmL1_2, \ - .LinkHotplug = mHotplug, \ - .MiscControls = { \ - .LinkSafeMode = mMaxLinkCap, \ - .ClkPmSupport = mClkPmSupport, \ - .TurnOffUnusedLanes = 1, \ - }, \ - } +#define MPIO_PORT_DATA_INITIALIZER_PCIE(mPortPresent, mDevAddress, mDevFunction, mHotplug, \ + mMaxLinkSpeed, mMaxLinkCap, mAspm, mAspmL1_1, \ + mAspmL1_2, mClkPmSupport) \ + { \ + .PortPresent = mPortPresent, \ + .DeviceNumber = mDevAddress, \ + .FunctionNumber = mDevFunction, \ + .LinkSpeedCapability = mMaxLinkSpeed, \ + .LinkAspm = mAspm, \ + .LinkAspmL1_1 = mAspmL1_1, \ + .LinkAspmL1_2 = mAspmL1_2, \ + .LinkHotplug = mHotplug, \ + .MiscControls = { \ + .LinkSafeMode = mMaxLinkCap, \ + .ClkPmSupport = mClkPmSupport, \ + .TurnOffUnusedLanes = 1, \ + }, \ + } +#endif +#ifndef MPIO_DDI_DATA_INITIALIZER +#define MPIO_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHdpIndex) \ + { \ + .ConnectorType = mConnectorType, \ + .AuxIndex = mAuxIndex, \ + .HdpIndex = mHdpIndex, \ + } #endif void opensil_mpio_per_device_config(struct device *dev) @@ -153,12 +171,15 @@ void opensil_mpio_per_device_config(struct device *dev) } } - static uint32_t slot_num; const uint32_t domain = dev_get_domain_id(dev); const uint32_t devfn = dev->path.pci.devfn; const struct drivers_amd_opensil_mpio_config *const config = dev->chip_info; - printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", - domain, PCI_SLOT(devfn), PCI_FUNC(devfn)); + static int ddi_port = 0; + if (is_pci(dev)) + printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", + domain, PCI_SLOT(devfn), PCI_FUNC(devfn)); + else if (config->type == IFTYPE_DDI) + printk(BIOS_DEBUG, "Setting DDI port %u\n", ddi_port); if (config->type == IFTYPE_UNUSED) { if (is_dev_enabled(dev)) { @@ -170,9 +191,11 @@ void opensil_mpio_per_device_config(struct device *dev) return; } - static int mpio_port = 0; - MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST }; if (config->type == IFTYPE_PCIE) { + static uint32_t slot_num; + static int mpio_port = 0; + + MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST }; const MPIO_ENGINE_DATA engine_data = MPIO_ENGINE_DATA_INITIALIZER(MpioPcieEngine, config->start_lane, config->end_lane, @@ -194,14 +217,32 @@ void opensil_mpio_per_device_config(struct device *dev) port.Port = port_data; port.Port.MiscControls.SbLink = config->sb_link; + + port.Port.AlwaysExpose = 1; + port.Port.SlotNum = ++slot_num; + mpio_data->PcieTopologyData.PortList[mpio_port] = port; + /* Update TERMINATE list */ + if (mpio_port > 0) + mpio_data->PcieTopologyData.PortList[mpio_port - 1].Flags = 0; + mpio_port++; + } else if (config->type == IFTYPE_DDI) { + MPIO_DDI_DESCRIPTOR ddi = { .Flags = DESCRIPTOR_TERMINATE_LIST }; + const MPIO_DDI_DATA ddi_data = MPIO_DDI_DATA_INITIALIZER(config->ddi_connector, + config->aux, + config->hdp); + + if (ddi_port >= MAX_DDI_PORTS) { + printk(BIOS_WARNING, "Exceeded maximum number of DDI ports.\n"); + return; + } + + ddi.Ddi = ddi_data; + ddi_descriptor_list[ddi_port] = ddi; + /* Update TERMINATE list */ + if (ddi_port > 0) + ddi_descriptor_list[ddi_port - 1].Flags = 0; + ddi_port++; } - port.Port.AlwaysExpose = 1; - port.Port.SlotNum = ++slot_num; - mpio_data->PcieTopologyData.PortList[mpio_port] = port; - /* Update TERMINATE list */ - if (mpio_port > 0) - mpio_data->PcieTopologyData.PortList[mpio_port - 1].Flags = 0; - mpio_port++; } void opensil_mpio_global_config(void) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h index 227d6e8a97b..6e0514c30cc 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h @@ -5,6 +5,8 @@ #include +#define MAX_DDI_PORTS 5 + /* * PHOENIX MPIO mapping * PCIE0 -> [0-19] bridges 1.1-1.5 @@ -15,6 +17,7 @@ enum mpio_type { IFTYPE_UNUSED, IFTYPE_PCIE, IFTYPE_SATA, + IFTYPE_DDI, }; /* Sync with PCIE_HOTPLUG_TYPE */ @@ -46,6 +49,41 @@ enum pcie_aspm { L0sL1, }; +enum ddi_type { + ConnDP, + ConnEDP, + ConnSingleLinkDVI, + ConnDualLinkDVI, + ConnHDMI, + ConnDpToVga, + ConnDpToLvds, + ConnNutmegDpToVga, + ConnSingleLinkDviI, + ConnDpWithTypeC, + ConnDpWithTypeCWithoutRetimer, + ConnDpWithoutTypeC, + ConnEDPToLvds, + ConnEDPToLvdsSwInit, + ConnAutoDetect, +}; + +enum ddi_aux { + DdiAux1, + DdiAux2, + DdiAux3, + DdiAux4, + DdiAux5, + DdiAux6, +}; + +enum ddi_hdp { + DdiHdp1, + DdiHdp2, + DdiHdp3, + DdiHdp4, + DdiHdp5, + DdiHdp6, +}; struct drivers_amd_opensil_mpio_config { enum mpio_type type; uint8_t start_lane; @@ -58,6 +96,10 @@ struct drivers_amd_opensil_mpio_config { uint8_t aspm_l1_2 : 1; uint8_t clock_pm : 1; uint8_t sb_link : 1; + /* DDI specific */ + enum ddi_type ddi_connector; + enum ddi_aux aux; + enum ddi_hdp hdp; }; #endif /* OPENSIL_PHOENIX_POC_MPIO_CHIP_H */ diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil b/src/vendorcode/amd/opensil/phoenix_poc/opensil index 0f806f9815c..4b607108764 160000 --- a/src/vendorcode/amd/opensil/phoenix_poc/opensil +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil @@ -1 +1 @@ -Subproject commit 0f806f9815c5ed14d69acbc40202078af67964e8 +Subproject commit 4b607108764028252a0af32d39dd0968a98453b8 diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c index 7fdf5441dbb..0bc2192c903 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -5,7 +5,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -286,7 +288,7 @@ WEAK_DEV_PTR(lpc_bridge); static void configure_fch_acpi(SIL_CONTEXT *SilContext) { - FCHHWACPI_INPUT_BLK *fch_hwacpi_data = SilFindStructure(SilContext, SilId_FchHwAcpiP, 0); + FCHHWACPI_INPUT_BLK *fch_hwacpi_data = SilFindStructure(SilContext, SilId_FchHwAcpi, 0); FCHCLASS_INPUT_BLK *fch_data = SilFindStructure(SilContext, SilId_FchClass, 0); struct device *smb = DEV_PTR(smbus); @@ -340,6 +342,30 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) FCH_DEV_ENABLE(hid, 31); } +static void configure_promontory(SIL_CONTEXT *SilContext) +{ + PROMCLASS_DATA_BLK *prom_data = SilFindStructure(SilContext, SilId_PromClass, 0); + size_t prom_fw_size; + + if (!prom_data) + return; + + prom_data->PromInputBlk.PT21ClkPMEnable = CONFIG(PCIEXP_CLK_PM); + prom_data->PromInputBlk.PT21L1Enable = CONFIG(PCIEXP_ASPM); + prom_data->PromInputBlk.PT21L1ssEnable = CONFIG(PCIEXP_L1_SUB_STATE); + prom_data->PromInputBlk.PT21DisableUnusedPciePort = 1; + + prom_fw_size = efs_read_promontory_fw((void *)CONFIG_PROMONTORY_FW_ADDR); + if (prom_fw_size) { + prom_data->PromInputBlk.PT21FwInRamAddress = CONFIG_PROMONTORY_FW_ADDR; + prom_data->PromInputBlk.PT21FWLoading = 0; + prom_data->PromInputBlk.PT21RuninRam = 1; + } else { + prom_data->PromInputBlk.PT21FwInRamAddress = CONFIG_PROMONTORY_FW_ADDR; + prom_data->PromInputBlk.PT21FWLoading = 1; + } +} + void setup_opensil(void) { SIL_CONTEXT SilContext; @@ -362,6 +388,8 @@ void setup_opensil(void) configure_usb(&SilContext); configure_ccx(&SilContext); configure_fch_acpi(&SilContext); + if (CONFIG(SOC_AMD_PHOENIX_AM5)) + configure_promontory(&SilContext); } static void opensil_entry(SIL_TIMEPOINT timepoint) diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c index 74cd24ed81e..6de5dde2893 100644 --- a/util/amdfwtool/amdfwread.c +++ b/util/amdfwtool/amdfwread.c @@ -707,6 +707,7 @@ static int dump_efw(const embedded_firmware *fw_header) printf("\nMisc info"); printf("\n Promontory FW: %08x", fw_header->promontory_fw_ptr); printf("\n LP Promontory FW: %08x", fw_header->lp_promontory_fw_ptr); + printf("\n Promontory19 FW: %08x", fw_header->promontory19_fw_ptr); printf("\n Vendor ID: %04x", fw_header->vendor_id); printf("\n Board ID: %04x", fw_header->board_id); printf("\n ESPI0 Config: %02x", fw_header->espi0_config); diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 0234dac95d7..17b1c4a7626 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -291,6 +291,8 @@ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_USBDP, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_USBSS, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_USB4, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PROM19, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB}, + { .type = AMD_FW_PROM19, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB}, { .type = AMD_FW_INVALID }, }; @@ -838,6 +840,14 @@ static void integrate_firmwares(context *ctx, case AMD_FW_XHCI: romsig->xhci_entry = RUN_CURRENT(*ctx); break; + case AMD_FW_PROM21: + if (fw_table[i].inst == 0) + romsig->promontory_fw_ptr = RUN_BASE(*ctx); + break; + case AMD_FW_PROM19: + if (fw_table[i].inst == 0) + romsig->promontory19_fw_ptr = RUN_BASE(*ctx); + break; default: /* Error */ break; @@ -1241,6 +1251,15 @@ static void integrate_psp_firmwares(context *ctx, pspdir->entries[count].addr = RUN_CURRENT(*ctx); pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); + + /* Save as offsets in flash */ + if (fw_table[i].type == AMD_FW_PROM21 && fw_table[i].inst == 0) + ctx->amd_romsig_ptr->promontory_fw_ptr = + (uint32_t)RUN_OFFSET_MODE(*ctx, ctx->current, AMD_ADDR_REL_BIOS); + if (fw_table[i].type == AMD_FW_PROM19 && fw_table[i].inst == 0) + ctx->amd_romsig_ptr->promontory19_fw_ptr = + (uint32_t)RUN_OFFSET_MODE(*ctx, ctx->current, AMD_ADDR_REL_BIOS); + adjust_current_pointer(ctx, bytes, BLOB_ALIGNMENT); } @@ -1882,6 +1901,7 @@ int main(int argc, char **argv) ctx.amd_romsig_ptr->psp_bak_directory = 0; ctx.amd_romsig_ptr->promontory_fw_ptr = 0; ctx.amd_romsig_ptr->lp_promontory_fw_ptr = 0; + ctx.amd_romsig_ptr->promontory19_fw_ptr = 0; ctx.amd_romsig_ptr->vendor_id = 0; ctx.amd_romsig_ptr->board_id = 0; ctx.amd_romsig_ptr->ubu_table = 0; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 94852e53e9c..86010c1dfbd 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -133,6 +133,7 @@ typedef enum _amd_fw_type { AMD_FW_USBDP = 0xa4, AMD_FW_USBSS = 0xa5, AMD_FW_USB4 = 0xa6, + AMD_FW_PROM19 = 0xa7, AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ AMD_FW_GEC, AMD_FW_XHCI, @@ -193,7 +194,7 @@ typedef struct _embedded_firmware { uint32_t psp_bak_directory; uint32_t promontory_fw_ptr; uint32_t lp_promontory_fw_ptr; - uint32_t reserved_38h; + uint32_t promontory19_fw_ptr; uint32_t reserved_3Ch; uint8_t spi_readmode_f15_mod_60_6f; uint8_t fast_speed_new_f15_mod_60_6f; diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index ae72145d7d8..2405a014d62 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -413,6 +413,14 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, fw_type = AMD_FW_PROM21; subprog = 0; instance = 1; + } else if (strcmp(fw_name, "PROM19_FW_FILE") == 0) { + fw_type = AMD_FW_PROM19; + subprog = 0; + instance = 0; + } else if (strcmp(fw_name, "PROM19_FW_INS1_FILE") == 0) { + fw_type = AMD_FW_PROM19; + subprog = 0; + instance = 1; } else if (strcmp(fw_name, "LSDMA_FILE") == 0) { fw_type = AMD_FW_LSDMA; subprog = 0; diff --git a/util/amdfwtool/sbom.c b/util/amdfwtool/sbom.c index 4234afa0fc7..09e6a248df0 100644 --- a/util/amdfwtool/sbom.c +++ b/util/amdfwtool/sbom.c @@ -303,6 +303,7 @@ static const char *psp_fw_type_name(amd_fw_entry *entry) case AMD_FW_GMI3_PHY: return "AMD GMI3 PHY Firmware"; case AMD_FW_MPDMA_PM: return "AMD MPDMA PM Firmware"; case AMD_FW_PROM21: return "AMD Promontory 21 Firmware"; + case AMD_FW_PROM19: return "AMD Promontory 19 Firmware"; case AMD_FW_LSDMA: return "AMD LSDMA Firmware"; case AMD_FW_C20_MP: return "AMD C20 MP Firmware"; case AMD_FW_MINIMSMU: return "AMD Mini-SMU Firmware";