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Merge pull request #146 from AlexTawseArm/mleco-4409-corstone-315
MLECO-4409: Arm Corstone-315 support
2 parents e20d889 + 5126e7a commit a9f63ac

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‎.gitignore‎

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tmp/
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*.cbuild.yml
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*.cbuild-idx.yml
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*.cbuild-pack.yml
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*.cbuild-set.yml
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‎cmsis-pack-examples/README.md‎

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Target platforms supported:
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| Name | Type | IP | Examples |
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|-----------------------|---------------------|-----------------------------------------------|----------|
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| Arm® Corstone™-300 | Virtual or physical | Arm® Cortex®-M55 CPU | All |
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| Arm® Corstone™-300-U55 | Virtual or physical | Arm® Cortex®-M55 CPU with Arm® Ethos™-U55 | All |
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| Arm® Corstone™-300-U65 | Virtual or physical | Arm® Cortex®-M55 CPU with Arm® Ethos™-U65 | All |
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| Arm® Corstone™-310 | Virtual or physical | Arm® Cortex®-M85 CPU | All |
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| Arm® Corstone™-310 | Virtual or physical | Arm® Cortex®-M85 CPU with Arm® Ethos™-U55 | All |
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| Arm® Corstone™-310-U65 | Virtual or physical | Arm® Cortex®-M85 CPU with Arm® Ethos™-U65 NPU | All |
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| Name | Type | IP | Examples |
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|------------------------------|---------------------|-----------------------------------------------|----------|
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| Arm® Corstone™-300 | Virtual or physical | Arm® Cortex®-M55 CPU | All |
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| Arm® Corstone™-300-U55 | Virtual or physical | Arm® Cortex®-M55 CPU with Arm® Ethos™-U55 | All |
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| Arm® Corstone™-300-U65 | Virtual or physical | Arm® Cortex®-M55 CPU with Arm® Ethos™-U65 | All |
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| Arm® Corstone™-310 | Virtual or physical | Arm® Cortex®-M85 CPU | All |
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| Arm® Corstone™-310 | Virtual or physical | Arm® Cortex®-M85 CPU with Arm® Ethos™-U55 | All |
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| Arm® Corstone™-310-U65 | Virtual or physical | Arm® Cortex®-M85 CPU with Arm® Ethos™-U65 NPU | All |
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| Arm® Corstone™-315 | Virtual or physical | Arm® Cortex®-M85 CPU | All |
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| Arm® Corstone™-315-U65 | Virtual or physical | Arm® Cortex®-M85 CPU with Arm® Ethos™-U65 NPU | All |
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| Alif™ Ensemble™ E7 AI/ML Kit | Physical board | Arm® Cortex®-M55 CPU with Arm® Ethos™-U55 NPU | All |
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| STM32® F746G-Discovery| Physical board | Arm® Cortex®-M7 CPU | KWS |
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| NXP® FRDM-K64F | Physical board | Arm® Cortex®-M4 CPU | KWS |
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| STM32® F746G-Discovery | Physical board | Arm® Cortex®-M7 CPU | KWS |
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| NXP® FRDM-K64F | Physical board | Arm® Cortex®-M4 CPU | KWS |
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Use this import button to open the solution in Keil Studio Cloud: [![Open in Keil Studio](https://img.shields.io/badge/Keil%20Studio-Import-blue?logo=data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0iMS4wIiBlbmNvZGluZz0idXRmLTgiPz4NCjwhLS0gR2VuZXJhdG9yOiBBZG9iZSBJbGx1c3RyYXRvciAyNS40LjEsIFNWRyBFeHBvcnQgUGx1Zy1JbiAuIFNWRyBWZXJzaW9uOiA2LjAwIEJ1aWxkIDApICAtLT4NCjxzdmcgdmVyc2lvbj0iMS4xIiBpZD0iTGF5ZXJfMSIgeG1sbnM9Imh0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnIiB4bWxuczp4bGluaz0iaHR0cDovL3d3dy53My5vcmcvMTk5OS94bGluayIgeD0iMHB4IiB5PSIwcHgiDQoJIHZpZXdCb3g9IjAgMCA0NyAxNCIgc3R5bGU9ImVuYWJsZS1iYWNrZ3JvdW5kOm5ldyAwIDAgNDcgMTQ7IiB4bWw6c3BhY2U9InByZXNlcnZlIj4NCjxzdHlsZSB0eXBlPSJ0ZXh0L2NzcyI+DQoJLnN0MHtmaWxsOiNGRkZGRkY7fQ0KPC9zdHlsZT4NCjxwYXRoIGNsYXNzPSJzdDAiIGQ9Ik00LjcsN2MwLDIuMiwxLjQsNC4xLDMuNSw0LjFjMS44LDAsMy42LTEuNCwzLjYtNC4xYzAtMi44LTEuNy00LjItMy42LTQuMkM2LjIsMi45LDQuNyw0LjcsNC43LDcgTTExLjYsMC41DQoJaDIuOXYxM2gtMi45di0xLjNjLTAuOSwxLjEtMi4zLDEuNy0zLjcsMS43QzQsMTMuOSwxLjgsMTAuNiwxLjgsN2MwLTQuMywyLjctNi45LDYuMS02LjljMS41LDAsMi44LDAuNywzLjcsMS45VjAuNXoiLz4NCjxwYXRoIGNsYXNzPSJzdDAiIGQ9Ik0xOCwwLjVIMjF2MS4yYzAuMy0wLjQsMC43LTAuOCwxLjItMS4xYzAuNS0wLjMsMS4yLTAuNCwxLjctMC40YzAuOCwwLDEuNiwwLjIsMi4zLDAuNmwtMS4yLDIuOA0KCWMtMC40LTAuMy0xLTAuNC0xLjUtMC40Yy0wLjctMC4xLTEuMywwLjItMS44LDAuN0MyMSw0LjYsMjEsNS45LDIxLDYuOHY2LjdIMThWMC41eiIvPg0KPHBhdGggY2xhc3M9InN0MCIgZD0iTTI4LjIsMC41aDIuOXYxLjJjMC43LTAuOSwxLjktMS42LDMuMS0xLjZjMS4zLDAsMi42LDAuNywzLjIsMS45YzAuOS0xLjIsMi4yLTEuOSwzLjctMS45DQoJQzQyLjcsMCw0NCwwLjksNDQuNywyLjJjMC4yLDAuNCwwLjcsMS40LDAuNywzLjN2OC4xaC0yLjlWNi4zYzAtMS41LTAuMi0yLjEtMC4yLTIuM2MtMC4yLTAuNy0wLjktMS4yLTEuNy0xLjENCgljLTAuNywwLTEuMywwLjMtMS43LDAuOWMtMC41LDAuOC0wLjYsMS45LTAuNiwyLjl2Ni43aC0yLjlWNi4zYzAtMS41LTAuMi0yLjEtMC4yLTIuM2MtMC4yLTAuNy0wLjktMS4yLTEuNy0xLjENCgljLTAuNywwLTEuMywwLjMtMS43LDAuOWMtMC41LDAuOC0wLjYsMS45LTAuNiwyLjl2Ni43aC0yLjlMMjguMiwwLjV6Ii8+DQo8L3N2Zz4NCg==&logoWidth=47)](https://studio.keil.arm.com/?import=https://github.com/Arm-Examples/mlek-cmsis-pack-examples.git)
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a virtual environment and installing this with pip.
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```shell
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$ pip install opencv-python
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$ pip install opencv-python "numpy<2.0.0"
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```
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**NOTE**: The requirement for Python version is driven by the FVP executable. Versions <= 11.26 require
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### Working with Virtual Streaming Interface
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The object detection example for Arm Corstone-300 and Corstone-310 supports Virtual Streaming Interface (VSI).
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The object detection example supports the Virtual Streaming Interface (VSI) feature found in the FVPs for Arm Corstone-300, Corstone-310 and Corstone-315.
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This allows the locally installed FVP application (or an AVH instance) to read images in from a camera connected to
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your local machine and stream these over to the application running within the FVP.
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To run the VSI application, append the command line with the v_path argument. For example:
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#### Arm Corstone-300 + Arm Corstone-310
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```shell
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$ <path_to_installed_FVP> \
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-a ./out/object-detection-vsi/AVH-SSE-300-U55/Release/object-detection-vsi.axf \
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-C ethosu.num_macs=256 \
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-C mps3_board.v_path=./device/corstone/vsi/video/python/
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```
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#### Arm Corstone-315
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```shell
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$ <path_to_installed_FVP> \
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-a ./out/object-detection-vsi/AVH-SSE-315-U65/Release/object-detection-vsi.axf \
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-C ethosu.num_macs=256 \
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-C mps4_board.v_path=./device/corstone/vsi/video/python/
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```
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## Application output
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Once the project can be built successfully, the execution on target hardware will show output of

‎cmsis-pack-examples/device/corstone/corstone-device.clayer.yml‎

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for-context:
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- +AVH-SSE-300
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- +AVH-SSE-315
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- +AVH-SSE-300-U55
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- +AVH-SSE-315-U65
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files:
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- file: src/retarget.c
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- file: src/uart_cmsdk_apb.c
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- +AVH-SSE-300-U65
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- +AVH-SSE-315-U65
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- component: tensorflow::Machine Learning:TensorFlow:Kernel&Ethos-U
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- +AVH-SSE-310
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- +AVH-SSE-315

‎cmsis-pack-examples/device/corstone/src/BoardInit.cpp‎

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/** @brief Initialises the NPU IRQ */
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static void arm_ethosu_npu_irq_init(void)
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{
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#if defined(CORSTONE310_FVP)
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const IRQn_Type ethosu_irqnum = (IRQn_Type)NPU0_IRQn;
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#else
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#if defined(CORSTONE300_FVP)
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const IRQn_Type ethosu_irqnum = (IRQn_Type)ETHOS_U55_IRQn;
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#else
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const IRQn_Type ethosu_irqnum = (IRQn_Type)NPU0_IRQn;
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/* Register the EthosU IRQ handler in our vector table.
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void* const ethosu_base_address = (void*)(NPU0_APB_BASE_NS);
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#if defined(CORSTONE300_FVP)
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void* const ethosu_base_address = (void*)(ETHOS_U55_APB_BASE_S);
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#else
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void* const ethosu_base_address = (void*)(NPU0_APB_BASE_NS);
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debug("Cache arena: 0x%p\n", get_cache_arena());

‎cmsis-pack-examples/device/corstone/src/uart_cmsdk_apb.c‎

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/*
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* SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its
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* SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its
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* affiliates <[email protected]>
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* SPDX-License-Identifier: Apache-2.0
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*
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#include "uart_config.h"
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#include "uart_stdout.h"
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/* Platform dependent files */
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#include "RTE_Components.h" /* Provides definition for CMSIS_device_header */
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#include CMSIS_device_header /* Gives us IRQ num, base addresses. */
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#include <stdio.h>
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__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
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#define CMSDK_UART0_BASE UART0_BASE_NS
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#define CMSDK_UART0 ((CMSDK_UART_TypeDef*)CMSDK_UART0_BASE)
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‎cmsis-pack-examples/device/corstone/src/uart_config.h‎

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/*
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* SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its
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* SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its
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#define SYSTEM_CORE_CLOCK (25000000)
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‎cmsis-pack-examples/kws/kws.cproject.yml‎

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- file: linker/mps4-sse-315.sct
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‎cmsis-pack-examples/kws/linker/mps3-sse-300.sct‎

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; Copyright (c) 2021-2022 Arm Limited. All rights reserved.
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; SPDX-FileCopyrightText: Copyright 2021-2022, 2024 Arm Limited and/or its affiliates <[email protected]>
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; SPDX-License-Identifier: Apache-2.0
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;
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; Licensed under the Apache License, Version 2.0 (the "License");
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; *************************************************************
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; *** Scatter-Loading Description File ***
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; *************************************************************
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; Please see docs/sections/appendix.md for memory mapping
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; information.
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;
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; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR
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; sections => activation buffers and the model should

‎cmsis-pack-examples/kws/linker/mps3-sse-310.sct‎

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; Copyright (c) 2021-2022 Arm Limited. All rights reserved.
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; SPDX-FileCopyrightText: Copyright 2021-2022, 2024 Arm Limited and/or its affiliates <[email protected]>
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; SPDX-License-Identifier: Apache-2.0
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; Please see docs/sections/appendix.md for memory mapping
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; information.
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;---------------------------------------------------------
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; First load region (SRAM/BRAM) 2MiB region
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;---------------------------------------------------------

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