Interrupt flag latency - Test C

[theklap]

Does this behavior only occur during a DMC DMA and with opcode 0x20? I am confused by the comment:
"; Surprise! the IRQ DOES occur after the branch!".

The previous tests say:
"; And hey, if you pass this one, keep in mind that I only test with BNE here, but this applies to every branch, not just BNE."

Any clarification you can give would be beneficial.

JSR $4013
;[DMC DMA. 4 cycles. Data bus = $90]
;(put cycle) Read Opcode: $90
; poll for interrupts, Interrupt will occur.
;(get cycle) Read Operand: $90
;(put cycle) Dummy read $4015.
; (transition from put to get: the Frame Counter Interrupt flag is cleared)
; poll for interrupts, interrupt will not occur.
;(get cycle) Dummy read.

; Surprise! the IRQ *DOES* occur after the branch!